Military Applications

Radar has been a foundational technology area in which the semiconductor industry has played a large role for the last two decades. In today's modern radar systems, Active Electronically Scanned Array (AESA) is the most popular architecture. Going forward, next-generation radar architectures such as digital phased array and synthetic aperture radar (SAR) with ground moving target indicator (GMTI) will be the emerging technology. To achieve this, parameters such as high-performance data processing, ultra-wide bandwidth, high dynamic range, and adaptive systems needed for diverse mission requirements are some of the most common challenges to system designers. An FPGA is an ideal, and in some cases necessary, solution in addressing these challenges. Using floating-point technology with Intel® Stratix® FPGA series and variable-precision digital signal processing (DSP) allows the designer to define the needed precision for each stage of the design. Logic and DSP resources are used efficiently while reducing power consumption.

In the AESA architecture shown in the figure below, one can easily identify several stages where an FPGA is necessary and where an FPGA provides a significant processing advantage.

The 28 nm Stratix® V FPGAs address the unique design requirements of radar and advanced sensor technologies. With 825 Gbps full-duplex serial transceiver bandwidth, large DSP counts, excellent signal integrity, highly scalable embedded processing blocks, and logic density leadership up to 950K logic elements (LEs), Stratix® V FPGAs offer true system-on-chip (SoC) possibilities for military radar and sensor designs.

With next-generation Intel® Arria® 10 and Intel® Stratix® 10 devices, the large DSP counts will be supplemented with the addition of hard floating-point IEEE-754 single precision DSP blocks. This will allow up to 1.5 TeraFLOPs in Intel® Arria® 10 FPGAs and up to 10 TeraFLOPs in Intel® Stratix® 10 FPGAs. Designers can infer these blocks using the OpenCL™ flow, DSP Builder for Intel FPGAs, and other Intel FPGA intellectual property (IP) blocks.

To enable shorter development time, Intel complements our silicon solutions with IP cores, reference designs, development kits, and system-level design tools. For specific radar reference designs and radar application support, please contact us.

In electronic warfare systems, key drivers for continuous enhancements are electronic counter-counter-measures (ECCM), stealth technologies, closely interlinked smart sensor networks, and intelligent guided weapons. These systems must be able to rapidly analyze and respond to multiple threats in very short time frames. In attempting to find target signatures in broadband noise, architects are seeking to perform complex processing such as fast Fourier transforms (FFTs), Cholesky decomposition, and matrix multiplication. Multiple software-generated waveforms are then transmitted to provide false targets, while powerful wideband signals provide overall cover. These shifting tactical responses require agile, high-performance processing. The entire system frequently resides in an airborne platform and must meet strict requirements for heat dissipation along with size, weight, power, and cost (SWaP-C) constraints.

A typical system design, uses a channelizer and inverse-channelizer to process high-bandwidth input signals. The number of channels are flexible so system designers can allocate hardware resources versus system performance as needed.

FPGAs offer an ideal solution to these performance requirements in the critical high-speed processing-intensive paths, a typical electronic warfare system with different electronic attack (EA) techniques.

Floating-Point Performance at Minimum Power

Electronic warfare designers can optimize digital signal processing (DSP) resources while still meeting SWaP-C constraints at the highest energy efficiency (GFLOPS/Watt) in any FPGA device across the industry. Using FPGA tools from Intel, DSP pipelines can be implemented quickly and optimized to up to 1.5 TFLOPS on Intel® Arria® 10 FPGAs and up to 10 TFLOPS on Intel® Stratix® 10 FPGAs.

Sensor and Backplane Interface

Stratix® V FPGAs have transceivers with speeds to 28 Gbps. A complete portfolio of transceivers is available to support a wide variety of backplane interfaces at minimum latency.

Shorter Time to Market and Less Engineering Risk

Intel has a complete set of intellectual property (IP) cores, reference designs, development kits, and system-level design tools. For specific electronic warfare reference designs and support, please contact us.

Today’s secure communications devices are faced with a number of design challenges. Wireline products must meet aggressive demands for data bandwidth to achieve 40-Gbps and 100-Gbps throughput, while often providing a tamper-resistant platform for cryptographic services for applications such as the JIE. Wireless products are developed under strict requirements for reduces size, weight, and power (SWaP) to enable next-generation mobility for military radios that can simultaneously support multiple waveforms such as SRW, WNW, and MUOS.

Secure Communications Systems

Secure communications design challenges apply to wired and wireless systems. Cryptographic functionality is an additional problem that is common to both systems.

Wireline Secure Communication

Information assurance systems with cryptographic capabilities including the Global Information Grid (GIG) support network performance in 40G to 100G and beyond. Net-centricity insures that what the warfighter sees on the ground can be linked to airborne and ground based assets.

Network Encryptor

All the core functions of a typical network encryptor can be implemented in Intel FPGAs within the tamper boundary. The 28 nm Stratix® V FPGA provides up to 930 Gbps of transceiver bandwidth at the lowest power consumption with support for over 50 industry-standard protocols. Large DSP counts, scalable embedded processing, and logic density leadership offer true system-on-programmable-chip (SoPC) for wireline secure communications. The Intel® Arria® 10 SoC further reduces power, adds security features, and provides a dual-core ARM* Cortex*-A9 hard processor system for control plane processing.

Wireless Secure Communication

Enhanced wireless radios require interoperability and security using commercial, AES, Suite A, and Suite B encryption algorithms. These enhanced radios link firefighters, emergency, medical, and law enforcement systems together while optimizing size, weight, power and cost (SWaP-C). Next generation military-grade trusted communications and SDR platforms must generate compatible waveforms, assuring operational compatibility while at the same time supporting multiple platforms and missions with field update capability. Intel®FPGAs enable wireless communications systems to meet these challenges.

Software Defined Radio

Intel® Cyclone® V SoC meets the demands of the lowest system cost and power, and the Intel® Arria® V SoC balances cost and performance. Intel SoC FPGAs consolidate your overall footprint with embedded dual-core ARM* A9 cores featuring 2.5 MIPS of Dhrystone performance.

Cryptographic Capabilities

Strong encryption is key to ensuring communications and data security at ever increasing data throughput rates. Strong cryptographic algorithms implemented on FPGAs that are secure by design provide the foundation for trusted information assurance systems.

The Cyclone III LS FPGA with design separation capability enables high security at low power. Information assurance platforms benefit from the low-cost, low-power Cyclone® V FPGA, while data rates of 100 Gbps and beyond can be achieved with the Stratix® V and Intel® Arria® 10 FPGAs.

To meet today's market demands, Intel offers the following devices qualified to operate at military temperatures:

• FPGAs 
  • Intel® Arria® 10 10AX660, 10AX570, 10AX480, 10AS480, 10AX220, 10AX160 military-grade -3 speed-grade devices in selected packages.
  • Stratix® V 5SGXA7, 5SGSD5 military-grade -4 speed-grade devices in selected packages.
  • Stratix® IV EP4SGX70, EP4SGX110, EP4SGX180, EP4SGX230, and EP4SE230 military-grade -3 speed-grade devices in selected packages.

The table below lists the temperature ranges for these devices.

Intel characterizes current industrial devices when operating over the military temperature range. These devices operate within specification, but run to a reduced speed grade timing model. For details about designing with and using these devices, refer to the related documentation indicated in the tables below.

For additional details regarding Intel's military temperature offerings, contact your local sales office or distributor.

Product Families Supported

The table below lists the military temperature offerings for Arria 10 FPGAs and SoCs.

For additional details regarding Altera's military temperature offerings and characterization report, contact your local sales office or distributor.

Intel works closely with commercial off-the-shelf (COTS) board partners to assure that customers can easily deploy the latest validated intellectual property (IP) onto proven production boards to lower system design and schedule risk when implementing complex high-performance systems. We can help with board and mezzanine-card selection to meet specific needs, device-type requirements, and design-time constraints. Our COTS partner ecosystems encompass development software for hardware and FPGA interfaces that utilize advanced application programming interfaces (APIs) and high-level languages. Our COTS partner ecosystems use Intel® Quartus® Prime Software along with DSP Builder for Intel® FPGAs (Advanced Blockset) for board design implementation as well as proprietary Intel and third-party software.

Intel's military COTS board partners include:

Aerospace and military designers face a long list of challenges, including the need for high performance, a broad operating envelope, and a long system life, as well as the added constraints of limited system size and power budgets. Intel FPGAs enable designers to meet the requirements of the aerospace and military markets by supplying enhanced off-the-shelf FPGAs.

Enhanced Off-the-Shelf Silicon

Intel FPGAs meet strict size, weight, and power requirements (SWaP) with high tolerance to humidity, shock, and vibration along with lead-solder available on all families.

Military Temperature Support

The Intel Stratix® series of FPGAs is available in extended military temperatures (‑55°C to 125°C).

SEU Detection and Mitigation

Intel’s automatic cyclic redundancy check (CRC) compiler for the configuration RAM automatically checks for changes in configuration that might occur from a single-event upset (SEU). See SEU Mitigation.

Radar, secure communications, and electronic warfare all have at their roots in high-performance digital signal processing (DSP) chains with a performance range from one GFLOPS to ten TFLOPS. Achieving this level of performance, while still maintaining reasonable size, weight, and power (SWaP), is a challenge.

System architects often develop their concepts and models in MathWorks's MATLAB, then a separate team quantizes the mathematical models for execution in fixed-point-capable hardware. This quantization step often introduces deviation from original model and suffers from possible dynamic range constraints or other system issues.

Intel® Arria® 10 and Intel® Stratix® 10 FPGAs will offer the industry highest GFLOPS/Watt ratio to help maintain SWaP. An IEEE 754- compliant floating-point processing chain can significantly reduce the processing burden, reducing the need for repeated normalization, and consequently increase the hardware efficiency. The floating-point capability of FPGAs can eliminate the quantization step between MATLAB and hardware implementation while maintaining the designer's original system specification. Intel® Arria® 10 and Intel® Stratix® 10 FPGAs will offer up to 1.5 & 10 TFLOPs respectively.

The following figure highlights some of the high-performance DSP capabilities in Stratix® V FPGAs. These include integrated coefficient registers, hard pre-adders, and three multiplier modes for flexibility. The DSP architecture along with DSP Builder for Intel FPGAs (Advanced Blockset) with fused data-path flow saves memory and routing resources while enabling designers to choose the precise blend of precision, utilization, and power.

18-bit and High-Precision Modes

Intel offers solutions, reference designs, and technical support to address military DSP applications. For more details, please contact us.

The RTCA DO-254/Eurocae ED-80 standard provides guidance for design assurance of airborne electronic hardware, from conception through initial certification and subsequent post certification product improvements to ensure continued airworthiness. DO-254 defines objectives that must be met by avionics equipment manufacturers according to EASA and FAA guidelines.

The RTCA DO-254 standard defines five levels of criticality from level A (highest) to level E (lowest). These design assurance levels are required for all civil airborne electronic hardware. More recently, military airborne applications such as A400M are now requiring DO-254 compliance.

To support the DO-254 certification process, Intel and its partners are proposing a complete set of tools and intellectual property (IP) that provides the data to present to the certification authority (see the figure below). Intel's experience with developers of airborne systems yields the following recommendations, as shown in the figure below.

Full Design Cycle Partner Network Solutions

Intel Partners in DO-254 Certifiable IP

The following IP cores are either being assessed for certification or are currently going through a documentation and certification process for Intel customers. Each of these IP cores, and several others, represent customer opportunities to undergo certification with support of Intel and IP partners (see Tables below).

What Customers are Saying About Intel's DO-254 Efforts

“Intel is a member of the DO-254 Users Group, since its creation in 2004, to unite the industry efforts in Europe. Altera, with the NIOS II_SC for DO-254, has made all the necessary efforts to understand the objectives for the requirements, development, production, and verification data for their NIOS II_SC processor.”

Lionel Burgaud
DO-254 Group Founder and Chairman

“We have involved Altera and Hcell Engineering since the beginning of our project to have the right level of confidence and documentation to present to EASA.”

Jerome Papineau
Program Manager at Thales Aerospace

“Together with the Cyclone® II and Cyclone II FPGAs and Nios® II embedded processor from Intel, we are able to address application requirements for very compact design of distributed embedded systems and smart sensor/actuator modules, that otherwise would require several components—thus reducing system cost and increasing reliability.”

Guenter Motzet
Director Chip IP Design from TTTech

Military communication and weapons systems are now overwhelmingly composed of high density, modern electronic components. Developing an edge, or competitive advantage, in the military marketplace necessarily requires taking advantage of the latest technologies, fastest processing, and the highest integration of analog and digital processes to reduce detection and response times in intelligence systems and military equipment.

These same systems, however, are often brought into service and maintained over time periods that are many multiples, or even orders of magnitude, longer than the constituent components of these systems. This inevitably creates the problem of component obsolescence, which is a primary issue in the field of logistics, and fuels entire industries of component and product emulation, reverse engineering, and code transfer and qualification.

End of Life Strategies, Including Selecting the Lowest Risk Vendor

Obsolescence costs, especially for unscheduled product discontinuation or vendor dissolution due to bankruptcy or acquisition, cannot be avoided completely. However dual-sourcing and a few other strategies including vendor support agreements, 'Last Time Buys,' and inventory banking through distributors, have been used with various degrees of supportability and cost success. An additional strategy is to perform Past Performance Assessments of vendors based on product support, and selecting the lowest risk vendor.

Arguably, this strategy is not used widely enough in defense acquisitions. Traditional supplier profiles and past performance do look at a vendor’s history, financial stability, and risk of the supplier as an on-going concern. However, these profiles don’t necessarily look at the business structure, decisions, and factors that lead to product support and supportability decisions of their components in the long term.

Assessing Product Support Risk

The FPGA Product Support and EOL as Past Performance Indicators White Paper (PDF) offers several statistical metrics with which to evaluate an FPGA provider’s history of product support based on 30 years of FPGA development and product history. A full data set to use for developing your own metrics is available on the Military Portal. An example of one of these metrics is shown in the diagram below.