GTS Transceiver Dual Simplex Interfaces User Guide

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ID 825853
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Understanding and Planning Dual Simplex Interfaces 4. Implementing Dual Simplex Interfaces 5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide
4. Implementing Dual Simplex Interfaces x
4.1. Generating the Simplex IP 4.2. Using the Dual Simplex Assignment Editor 4.3. Generating the Dual Simplex IP 4.4. Connecting the Dual Simplex IP 4.5. Verifying the Dual Simplex IP Implementation
1. Introduction
2. Overview
3. Understanding and Planning Dual Simplex Interfaces
4. Implementing Dual Simplex Interfaces
5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide

2. Overview

The GTS transceivers in Agilex™ 5 FPGAs support various simplex protocol implementations. In simplex mode, the GTS channel is unidirectional and that leaves an unused transmitter or receiver. Using the dual simplex mode, you can utilize the unused transmitter or receiver channel to implement another independent simplex protocol as shown in the following figure.
Figure 1. Channel Utilization in Simplex and Dual Simplex Modes
The dual simplex (DS) mode supports the following combination of simplex protocol IPs 1.
Table 1.  Supported Protocol IP Combinations for Dual Simplex Mode
Receiver IP Transmitter IP
SDI HDMI DisplayPort SerialLite IV 2 JESD204C2 JESD204B2
SDI Yes Yes Yes No No No
HDMI Yes Yes Yes No No No
DisplayPort Yes Yes Yes No No No
SerialLite IV2 No No No Yes Yes Yes
JESD204C2 No No No Yes Yes Yes
JESD204B2 No No No Yes Yes Yes
Figure 2. Dual Simplex Mode Implementation High-Level StepsDS mode can be implemented in the Quartus® Prime Pro Edition software by generating a DS IP based on the simplex protocol IPs, and using the DS IP for RTL design as highlighted in the following figure. The generated DS IP comprises of the individual simplex IPs that you want to pair in DS mode and use in your design.
1 DS mode is only supported for the specified simplex protocols, and not for custom TX/RX modes with the GTS PMA/FEC Direct PHY Intel FPGA IP
2 DS mode is not supported for this IP in the current release of the Quartus® Prime Pro Edition software.
Level Two Title