GTS Transceiver Dual Simplex Interfaces User Guide

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ID 825853
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. Understanding and Planning Dual Simplex Interfaces 4. Implementing Dual Simplex Interfaces 5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide
4. Implementing Dual Simplex Interfaces x
4.1. Generating the Simplex IP 4.2. Using the Dual Simplex Assignment Editor 4.3. Generating the Dual Simplex IP 4.4. Connecting the Dual Simplex IP 4.5. Verifying the Dual Simplex IP Implementation
1. Introduction
2. Overview
3. Understanding and Planning Dual Simplex Interfaces
4. Implementing Dual Simplex Interfaces
5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide

4.5. Verifying the Dual Simplex IP Implementation

This section describes the steps to synthesize and verify the previously connected dual simplex IP in your design.
To synthesize and verify the dual simplex IP, follow these steps:
  1. Synthesize the design by running the Analysis & Synthesis step in the Quartus® Prime Pro Edition software Compilation Dashboard. The following figure shows the dashboard after a successful Analysis & Synthesis compile.
    Figure 25. Successful Analysis & Synthesis Compile
  2. You can verify the DS IP in simulation upon successful completion of the Analysis & Synthesis. The following figure shows an example of the DS IP passing simulation with the HDMI testbench.
    Note: You can simulate the DS IP after the Analysis & Elaboration stage completes.
    Figure 26. DS IP Simulation Results
  3. Perform a pin placement for the design. In the Quartus® Prime Pro Edition software, click Assignments > Pin Planner to open the pin planner tool. Set the RX and TX pins to the same bank to combine the simplex TX and simplex RX pins to the same physical channel (for example Bank 4C) as shown in the following figure.
    Figure 27. Pin Placement for the DS IP Design
  4. Run a full compilation of the DS design implementation as shown in the following figure.
    Figure 28. Compile of the DS IP Design
  5. Once the compile completes successfully, you can check the pin placement of the design by clicking the Fitter > Plan > Open Compilation Report step in the Quartus® Prime Pro Edition software Compilation Dashboard as shown in the following figure.
    Figure 29. Successful Compilation of the DS IP Design
    You can then verify that the Quartus® Prime Pro Edition software placed the simplex TX and simplex RX pins according to the Pin Planner settings and the pins are successfully combined by checking the reports as shown in the following figures.
    Figure 30. Input Pins Placement Report for DS IP Design
    Figure 31. Output Pins Placement Report for DS IP Design
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