GTS Interlaken Intel® FPGA IP Design Example User Guide

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ID 819203
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS Interlaken FPGA IP Design Example User Guide Archives 4. Document Revision History for GTS Interlaken IP Design Example User Guide
1. Quick Start Guide x
1.1. Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the GTS Interlaken IP Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. GTS Interlaken FPGA IP Design Example User Guide Archives
4. Document Revision History for GTS Interlaken IP Design Example User Guide

1.2. Generating the Design

Figure 3. Procedure
Follow these steps to generate the design example and testbench:
  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or click File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family Agilex™ 5 (D-Series/E-Series) and select device with GTS for your design.
  3. In the IP Catalog, locate and double-click GTS Interlaken Intel FPGA IP. The New IP Variant window appears.
  4. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click OK. The parameter editor appears.
    Figure 4. Example Design Tab
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the Example Design tab, select the Simulation option to generate the testbench. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  8. For Generated HDL Format, both Verilog and VHDL option is available.
  9. Click Generate Example Design. The Select Example Design Directory window appears.
  10. If you want to modify the design example directory path or name from the defaults displayed (intel_ilk_gts_0_example_design), browse to the new path and type the new design example directory name.
  11. Click OK.
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