GTS Interlaken Intel® FPGA IP Design Example User Guide

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ID 819203
Date 1/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS Interlaken FPGA IP Design Example User Guide Archives 4. Document Revision History for GTS Interlaken IP Design Example User Guide
1. Quick Start Guide x
1.1. Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the GTS Interlaken IP Design Example Testbench 1.5. Compiling and Configuring the Hardware Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Design Example Flow 2.3. Interface Signals 2.4. Register Map 2.5. Reset
1. Quick Start Guide
2. Design Example Description
3. GTS Interlaken FPGA IP Design Example User Guide Archives
4. Document Revision History for GTS Interlaken IP Design Example User Guide

2. Design Example Description

The design example demonstrates the functionalities of the Interlaken IP core.

Section Content
Design Example Components
Design Example Flow
Interface Signals
Register Map
Reset

Level Two Title