Performance Monitor FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

Download PDF
ID 817760
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Performance Monitor (PMON) FPGA IP 2. Introduction to the Performance Monitor (PMON) IP 3. Performance Monitor IP Functional Description 4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP 5. Performance Monitor (PMON) FPGA IP Interface Signals 6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide A. Performance Monitor (PMON) Library Functions
1. About the Performance Monitor (PMON) FPGA IP x
1.1. Release Information
3. Performance Monitor IP Functional Description x
3.1. AXI4 Traffic Limitations
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP x
4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP 4.2. Parameterizing the Performance Monitor (PMON) FPGA IP 4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions 4.4. Simulation Support
5. Performance Monitor (PMON) FPGA IP Interface Signals x
5.1. Clock and Reset Signals 5.2. AXI4 Interface Signals 5.3. AXI4-Lite Interface Signals 5.4. Registers
5.4. Registers x
5.4.1. Global Discovery Registers 5.4.2. Global Control Registers 5.4.3. Global Status Registers 5.4.4. Unit Discovery 5.4.5. Unit Control Registers 5.4.6. Unit Status Registers 5.4.7. Counter Control Registers 5.4.8. Data Registers 5.4.9. AXI4 Event Support
A. Performance Monitor (PMON) Library Functions x
A.1. Derived Parameters from PMON IP
1. About the Performance Monitor (PMON) FPGA IP
2. Introduction to the Performance Monitor (PMON) IP
3. Performance Monitor IP Functional Description
4. Creating and Parameterizing the Performance Monitor (PMON) FPGA IP
5. Performance Monitor (PMON) FPGA IP Interface Signals
6. Document Revision History for the Performance Monitor (PMON) FPGA IP User Guide
A. Performance Monitor (PMON) Library Functions

4.1. Creating a Quartus® Prime Pro Edition Project for the Performance Monitor (PMON) FPGA IP

You can parameterize and generate the Performance Monitor (PMON) IP using the Quartus® Prime Pro Edition software.
  1. Before you can generate the PMON IP, you must create a new project, as follows:
    1. Launch the Quartus® Prime Pro Edition software.
    2. Launch the New Project Wizard by clicking File > New Project Wizard.
    3. Type a name for your project in the Directory, Name, Top-Level Entity field.
    4. In the Project Type section, select Empty Project.
    5. In the Add Files section, click Next.
    6. On the Device tab, select Agilex™ 7 (F-Series/M-Series/I-Series) or Agilex™ 5 (E-Series/D-Series) as the device family.
    7. Under Available Devices, select your choice of device and the desired speed grade.
    8. Click Next and follow the Wizard's prompts to finish creating the project.
  2. In the IP Catalog, open Library > Memory Interfaces and Controllers.
  3. Click Performance Monitor FPGA IP to launch the PMON parameter editor.
Level Two Title