4.3. Performance Monitor (PMON) FPGA IP Parameter Descriptions
The following table summarizes the PMON IP parameters.
Parameter | Range | Description |
---|---|---|
Remote access via JTAG | True, False | Choose whether to have access to Control and Status Registers (CSRs) via JTAG or through the AXI-Lite interface. The default value is False. |
Unit Monitor 0 | ||
Unit ID | 0-65335 | Set to differentiate instances of PMON in hardware and simulation via the Unit ID CSR value. The default value is 0. |
Counter Width | 33-63 | Specifies the counter width of the unit monitor data counters, in bits. Increasing the counter width values leads to larger area usage; reducing the width reduces the area usage of the monitor. |
Advanced Latency | True, False | Changes read and write latency to be monitored on a per-transaction basis rather than by number of outstanding transactions. If you enable this option per transaction latency binning and maximum latency can be tracked. If you disable this option maximum outstanding transactions can be tracked. If you enable this option the maximum number of outstanding transactions is 500 for Writes and 500 Reads with a maximum latency of 65,536 cycles. If you disable this option the maximum number of outstanding transactions is 65,536 and the maximum latency is limited to the maximum value the data counters can support (which is 2 Counter Width -1). |
AXI Interface | ||
Write ID Width | 1-18 | Specifies widths of AWID and BID ports of the AXI4 bus. The default value is 7. |
Write Address Width | 4-64 | Specifies width of AWADDR port of the AXI4 bus. The default value is 31.
Note: The minimum valid value equals floor(log2(N))+ 1 where N is the input value for the Write Data Width parameter.
|
Use AWLOCK | True, False | Enables AWLOCK port of the AXI4 bus. The default value is True. |
Use AWCACHE | True, False | Enables AWCACHE port of the AXI4 bus. The default value is True. |
Use AWQOS | True, False | Enables AWQOS port of the AXI4 bus. The default value is True. |
Use AWREGION | True, False | Enables AWREGION port of the AXI4 bus. The default value is False. |
Use AWUSER | True, False | Enables AWUSER port of the AXI4 bus. The default value is True. |
AWUSER Width | 1-64 | Specifies width of AWUSER port of the AXI4 bus. The default value is 8. |
Read ID Width | 1-18 | Specifies widths of ARID and RID ports of the AXI4 bus. The default value is 7. |
Read Address Width | 1-64 | Specifies width of ARADDR port of the AXI4 bus. The default value is 31. |
Use ARLOCK | True, False | Enables ARLOCK port of the AXI4 bus. The default value is True. |
Use ARCACHE | True, False | Enables ARCACHE port of the AXI4 bus. The default value is True. |
Use ARQOS | True, False | Enables ARQOS port of the AXI4 bus. The default value is True. |
Use ARREGION | True, False | Enables ARREGION port of the AXI4 bus. The default value is False. |
Use ARUSER | True, False | Enables ARUSER port of the AXI4 bus. The default value is True. |
ARUSER Width | 1-64 | Enables ARUSER port of the AXI4 bus. Specifies width of ARUSER port of the AXI4 bus. The default value is 8. |
Write Data Width | 8-192, 256-320, 512-576, 1024-1088 | Specifies width of write data. 2^N bits are mapped to the WDATA port and the remainder of the bits up to a maximum of 64 are mapped to the WUSER port. N is a integer ranging from 3 to 10. |
Read Data Width | 8-192, 256-320, 512-576, 1024-1088 | Specifies width of read data. 2^N bits are mapped to the RDATA port and the remainder of the bits up to a maximum of 64 are mapped to the RUSER port. N is a integer ranging from 3 to 10. |
Use BUSER | True, False | Enables BUSER port of the AXI4 bus. The default value is False. |
BUSER Width | 1-64 | Specifies width of BUSER port of the AXI4 bus. The default value is 8. |