MIPI D-PHY IP Release Notes: Agilex™ 5 FPGAs

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ID 817563
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 FPGA MIPI D-PHY IP Release Notes
1. Agilex™ 5 FPGA MIPI D-PHY IP Release Notes x
1.1. Agilex™ 5 FPGA MIPI D-PHY IP v3.1.0 1.2. Agilex™ 5 FPGA MIPI D-PHY IP v3.0.0 1.3. Agilex™ 5 FPGA MIPI D-PHY IP v2.2.0
1. Agilex™ 5 FPGA MIPI D-PHY IP Release Notes

1.3. Agilex™ 5 FPGA MIPI D-PHY IP v2.2.0

Table 15.  v2.2.0 2024.04.01
Description Impact
Verified in the Quartus® Prime software v24.1. Provides MIPI D-PHY IP support for Agilex™ 5 devices. The tables that follow summarize speed and feature support.
Note: This documentation is preliminary and subject to change.
Table 16.   Agilex™ 5 MIPI D-PHY IP Speed Support Summary
    Max Rate (Mbps) 4 5 6
Device Family Subcategory 4 5 6 S C T H S C T H S C T H
E-Series Device Group B Long reference/standard reference/ short reference 1 150 - 2500 1 150 - 2500 1 150 - 2500 1 X X X 2 X X X X 2 X X X X 2 X
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Long reference/standard reference/short reference is reference to the insertion loss condition from MIPI Alliance D-PHY specifications.
  • 2 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 17.   Agilex™ 5 MIPI D-PHY IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
MIPI D-PHY PPI bus width 16 X X X X X
8          
Skew Calibration RX and TX X X X X X
Alternate Calibration RX and TX X X X X X
Periodic Calibration TX X X X X X
Design Example   X X X X X
TX Equalization Mode Mode 1 X X X X X
Mode 2 X X X X X
Simulation External loopback simulation X X      
Simulators 1 VCS X X      
VCS-MX X X      
QuestaSim X X      
Xcelium X X      
Questa-Intel FPGA Edition X X      
Aldec Riviera-PRO          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
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