External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs

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Date 7/08/2024
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1. External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs
1. External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs x
1.1. External Memory Interfaces (EMIF) IP v6.2.0 1.2. External Memory Interfaces (EMIF) IP v6.1.0
1. External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 5 FPGAs and SoCs

1.2. External Memory Interfaces (EMIF) IP v6.1.0

Table 14.  v6.1.0 2024.04.01
Description Impact
Verified in the Quartus® Prime software v24.1. Provides external memory interface IP for DDR4, LPDDR4, and LPDDR5 external memory for Agilex™ 5 devices. The tables that follow summarize speed and feature support.
Note: This documentation is preliminary and subject to change.
Table 15.   Agilex™ 5 E-Series Device Group B (ES0) Fabric EMIF / HPS EMIF IP Speed Support Summary 3
      Max Rate (Mbps/MHz)   -4 -5 -6
Protocol Category Subcategory -4 -5 -6 Support Detail S C T H S C T H S C T H
DDR4 Memory Format Component 2400/1200 (1R) 1866/933 (1R) 1600/800 (1R)   X 1 X X 2 X X 1 X X 2 X X 1 X X 2 X
2400/1200 (2R) 1866/933 (2R) 1600/800 (2R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
LPDDR4 Memory Format Component 2667/1333 (1R) 2400/1200 (1R) 1866/933 (1R)   X 1 X X 2 X X 1 X X 2 X X 1 X X 2 X
2667/1333 (2R) 2400/1200 (2R) 1866/933 (2R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
LPDDR5 Memory Format Component 2400/1200 (1R) 2400/1200 (1R) 1866/933 (1R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
2400/1200 (2R) 2400/1200 (2R) 1866/933 (2R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Supports VCS and QuestaSim.
  • 2 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.
  • 3 The FMAX for this table is applicable to the following non-ES0 OPNs in the Quartus® Prime software version 24.1. The FMAX for these OPNs will be revised in a future version: A5EC043BB23AXXX, A5EC052BB23AXXX, A5EC065BB23AXXX, A5ED043BB23AXXX, A5ED052BB23AXXX, A5ED065BB23AXXX, A5EC043BB32AXXX, A5EC052BB32AXXX, A5EC052BB32AXXX, A5ED043BB32AXXX, A5ED052BB32AXXX, A5ED052BB32AXXX.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 16.   Agilex™ 5 E-Series Device Group B (ES0) Fabric EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X X
32, 32+ECC X X X X X
Controller Hard controller X X X X X
3DS 3DS          
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings          
Write preamble settings          
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings X X X X X
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example   X X X X X
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings X X X X X
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.

Table 17.   Agilex™ 5 E-Series Device Group B (ES0) HPS EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X X
32, 32+ECC X X X X X
Controller Hard controller X X X X X
3DS 3DS          
Design Example            
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings          
Write preamble settings          
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example            
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings X X X X X
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X X
1ch x16 X X X X X
2ch x16 X X X X X
4ch x16 X X X X X
Controller Hard controller X X X X X
Design Example            
DBI Read DBI          
Write DBI X X X X X
DM DM pins X X X X X
Preamble Read preamble settings X X X X X
Write preamble settings          
Postamble Read postamble settings X X X X X
Write postamble settings X X X X X
AXI access mode Fabric sync mode X X X X X
Fabric async mode X X X X X
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
Table 18.   Agilex™ 5 E-Series Device Group B Fabric EMIF / HPS EMIF IP Speed Support Summary 3
      Max Rate (Mbps/MHz)   -4 -5 -6
Protocol Category Subcategory -4 -5 -6 Support Detail S C T H S C T H S C T H
DDR4 Memory Format Component 2400/1200 (1R) 2133/1066 (1R) 1866/933 (1R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
2400/1200 (2R)

2133/1066

(2R) 		1866/933 (2R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
LPDDR4 Memory Format Component 2667/1333 (1R) 2667/1333 (1R) 2133/1066 (1R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
2667/1333 (2R) 2667/1333 (2R) 2133/1066 (2R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
LPDDR5 Memory Format Component 2400/1200 (1R) 2400/1200 (1R) 1866/933 (1R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
2400/1200 (2R) 2400/1200 (2R) 1866/933 (2R)   X 1 X X 2   X 1 X X 2   X 1 X X 2  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Supports VCS and QuestaSim.
  • 2 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.
  • 3 The FMAX for this table is applicable to the following non-ES0 OPNs in the Quartus® Prime software version 24.1: A5EC008BB23AXXX , A5EC013BB23AXXX, A5ED008BB23AXXX, A5ED013BB23AXXX, A5EC008BB32AXXX , A5EC013BB32AXXX, A5ED008BB32AXXX, A5ED013BB32AXXX, A5EC008BM16AXXX , A5EC013BM16AXXX, A5ED008BM16AXXX, A5ED013BM16AXXX, A5EA008BB23BXXX , A5EA013BB23BXXX, A5EB013BB23BXXX,A5EE008BB23BXXX ,A5EE013BB23BXXX.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 19.   Agilex™ 5 E-Series Device Group B Fabric EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X  
32, 32+ECC X X X X  
Controller Hard controller X X X X  
3DS 3DS          
Design Example   X X X X  
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings          
Write preamble settings          
AXI access mode Fabric sync mode X X X X  
Fabric async mode X X X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
4ch x16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
AXI access mode Fabric sync mode X X X X  
Fabric async mode X X X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
4ch x16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
AXI access mode Fabric sync mode X X X X  
Fabric async mode X X X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX X X      
ModelSim SE X X      
Xcelium X X      
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.

Table 20.   Agilex™ 5 E-Series Device Group B HPS EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC X X X X  
32, 32+ECC X X X X  
Controller Hard controller X X X X  
3DS 3DS          
Design Example            
DBI Read DBI X X X X  
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings          
Write preamble settings          
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR4 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
4ch x16 X X X X  
Controller Hard controller X X X X  
Design Example            
DBI Read DBI          
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
LPDDR5 Interface Width 1ch x32 X X X X  
1ch x16 X X X X  
2ch x16 X X X X  
4ch x16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X  
DM DM pins X X X X  
Preamble Read preamble settings X X X X  
Write preamble settings          
Postamble Read postamble settings X X X X  
Write postamble settings X X X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS          
VCS-MX          
ModelSim SE          
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
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