F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

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ID 816968
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 50G Ethernet Design Example Description 3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 50G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 50G Ethernet Design Example Description
3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

2.8. Design Example Interface Signals

The F-Tile Low Latency 50G Ethernet testbench is self-contained and does not require you to drive any input signals.

Table 8.  Hardware Design Example Interface Signals
Signal Direction Comments
clk_ref Input

This clocks the CDR in receive direction of the transceivers. Drive at 156.25 MHz.
clk_status Input CSR clock
i_clk_sys Input Input System PLL clock to F-Tile Low Latency 50G Ethernet Intel® FPGA IP.
i_clk_ref Input Drive at 156.625 MHz.
o_tx_serial[1:0] Output Transceiver PHY output serial data.
i_rx_serial[1:0] Input Transceiver PHY input serial data.
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