F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

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ID 816968
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 50G Ethernet Design Example Description 3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 50G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 50G Ethernet Design Example Description
3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

2.6. Hardware Testing

The hardware test project includes a JTAG to Avalon® memory-mapped master that allows interfacing with the IP and packet generator via System Console. A hwtcl library, which is generated alongside the design example, provides basic functionality such as reading and writing status and control registers, printing simple status reports, turning on or off loopback, and packet generation.

To access the IP via System Console, follow these steps:

  1. Program the device.
  2. In the System Console, change the working directory to hwtest. This folder is located under the hardware_test_design folder.
  3. Use the following command to open a connection to the JTAG master: 
    source main.tcl
  4. Use reg_read and reg_write to access the registers.
    Examples:
    1. To read register 0x100: reg_read 0x100
    2. To write 0xFF to register 0x100: reg_write 0x100 0xFF

Section Content
Test Procedure

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