F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

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ID 816968
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile Low Latency 50G Ethernet Design Example Description 3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Generating Tile Files 1.5. Simulating the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile Low Latency 50G Ethernet Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing 2.7. Design Example Registers 2.8. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-Tile Low Latency 50G Ethernet Design Example Description
3. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP Design Example User Guide

2.3.1. Design Components

Table 4.  Design Components
Component Description
F-Tile Low Latency 50G Ethernet Intel® FPGA IP

The F-Tile Low Latency 50G Ethernet Intel® FPGA IP , consists of MAC, PCS, and Transceiver PHY, with the following configuration:

  • Device Family: Agilex 7
  • Targeted Transceiver Tile: None
  • Ready Latency: 0 or 3
  • PHY reference frequency: 156.25MHz, 312.5MHz, or 322.266 MHz
  • Enable TX CRC Insertion: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable MAC stats counters: Optional
  • Enable Strict SFD check: Optional
  • Enable Flow Control: Optional
  • Number of queues in priority flow control: 1–8
  • Enable Native PHY Debug Master Endpoint: Optional
  • Enable JTAG to Avalon Master Bridge: Optional
F-Tile Reference and System PLL Clocks Intel® FPGA IP F-Tile Reference and System PLL Clocks Intel® FPGA IP generates transceiver and system PLL reference clocks.
Client Logic for Ethernet Packet Generator and Packet Monitor
Consists of:
  • Packet generator generates frames and transmit to the DUT.
  • Packet Monitor monitors TX and RX datapaths and displays the frames in the system console.
In-System Sources & Probes Intel® FPGA IP Source and probe signals, including system reset input signal.
Related Information
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