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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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1.2. Generating the Design Example
Generate the design example from the IP Parameter Editor.
Figure 3. Procedure
Figure 4. Example Design Tab in the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameter Editor
Follow these steps to generate the hardware design example and testbench:
- In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device family and device.
- In the IP Catalog, locate and select F-Tile Low Latency 100G Ethernet Intel® FPGA IP . The New IP Variation window appears.
- Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
- Click OK. The parameter editor appears.
- On the IP tab, specify the parameters for your IP variation. Refer to the Design Components table for information about specific IP core parameters.
- On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
- Under Target Development Kit select the Agilex 7 Transceiver Signal Integrity Development Kit (Production).
Note: The development kit that you select overwrites the device selection in step 1.
- Click the Generate Example Design button. The Select Example Design Directory window appears.
- If you want to modify the design example directory path or name from the defaults displayed (alt_e100_f_0_example_design ), browse to the new path and type the new design example directory name (<design_example_dir>).
- Click OK.