F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2.3.1. Design Components

Table 4.  Design Components
Component Description
F-Tile Low Latency 100G Ethernet Intel® FPGA IP

The F-Tile Low Latency 100G Ethernet Intel® FPGA IP with the following configuration:

  • Device Family: Agilex 7
  • Targeted Transceiver Tile: None
  • Ready Latency: 0 or 3
  • Enable RS-FEC: Optional
  • PHY reference frequency: 156.25MHz, 312.5MHz, or 322.266 MHz
  • Enable TX CRC Insertion: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable MAC stats counters: Optional
  • Enable Strict SFD check: Optional
  • Enable Flow Control: Optional
  • Number of queues in priority flow control: 1–8
  • Enable Native PHY Debug Master Endpoint: Optional
  • Enable JTAG to Avalon Master Bridge: Optional
F-Tile Reference and System PLL Clocks Intel® FPGA IP F-Tile Reference and System PLL Clocks Intel® FPGA IP generates transceiver and system PLL reference clocks.
Client Logic for Ethernet Packet Generator and Packet Monitor
Consists of:
  • Packet generator generates frames and transmit to the DUT.
  • Packet Monitor monitors TX and RX datapaths and displays the frames in the system console.
In-System Sources & Probes Intel® FPGA IP Source and probe signals, including system reset input signal.