5.5.6.5. Write Data Path

Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

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Date 4/01/2024

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5.5.6.5. Write Data Path

The following figure shows the main components of the write data path in the PHY.

Figure 157. Write Data Path High-Level Block Diagram

The write path is integrated by three main components, the DLL PHY, frequency ratio module, and the balance module. These three components together produce the data and command data to be sent to the memory devices during a write operation. The DLL PHY described in the previous section generates the reference clock used at the data/command output during write operation.

When using the combo PHY as a NAND interface, the clock ratio between the memory controller clock (clk_ctrl) and the PHY clock (clk_phy) is 1:2. In this case, the frequency ratio module performs the clock domain conversion by converting input signals with phase information (dfi_*_p0 and dfi_*_p1) into data/command signals (write*_h and write_*_l).

In the case of the SD/eMMC interface, the controller clock frequency is the same as the PHY clock, so the 1:2 clock domain translation is bypassed (that is, the ratio is 1:1). In this case, the phase0 input signals are used as the output signals (dfi_wrdata_p0 and dfi_wrcmd_p0).

The frequency ratio module produces two 8-bit data signals (write_data_l and write_data_h and two 1-bit command signals (write_cmd_l and write_cmd_h). In this initial stage, the input phase signals are synchronized with the clk_ctrl clock, while the output signals are synchronized with clk_phy. The low_freq_sel bit in the phy_ctrl_reg register must be configured to match the clock synchronization in the DFI interface at the output of the memory controller. An example of the clock frequency translation executed by the frequency ratio module is shown next. This example assumes that low_freq_sel is ‘1’ so this means that dfi_data_pX signals are aligned to the falling edge of the clk_ctrl clock.

Figure 158. Clock Domain Translation in Frequency Ratio Module

Note: The frequency ratio module is used to translate the clock domain of all of the dfi_*_p0/p1 phase input signals (not only data and command signals). For all these signals, the clock domain translation is done in the same way as explained above. Similarly, the ratio translation is bypassed in SD/eMMC mode and in the p0 signal is transferred directly to the output of the frequency ratio module.

The last component in the write data path is the ‘balance module’ which is used to create a delayed balanced data/command output with minimum skew among each one of the output data/command bits. This balance is performed at bit level having 8 modules to process the 8-bit data and one additional module for the command (used for SD/eMMC). Each individual balance module receives the data high and low signals coming from the frequency ratio module and produces a single output bit whose behavior depends on the PHY operation mode.

In the case that the PHY operation mode requires use of a DDR interface, the output bit of this module consists of the serialization of the high and low input bits transmitting the low input bit first. In this case, the module requires creation of a clock that is exactly ¼ cycle out of phase with clk_phy. To generate the clk_wr clock signal , this module uses digital DLL and a delay adder to produce this signal with the appropriate delay relative to the clk_phy.

The following diagram shows the internal logic of the balance module in the write data/command path.

Figure 159. Balance Module Block Diagram in Write Data Path

In the previous figure, the write_data_h and write_data_l input signals are synchronized with clk_phy(same for the write_cmd signals). Alternatively, for data it is possible to use as input loop back signals for which the selection can be done using the lpbk_en bit in the phy_gate_lpbk_ctrl_reg register. For command, the loopback_en signal is tied to 0.

Continuing moving forward in the data path, you can add an additional clk_phy clock cycle delay to the output data/command. Use the data_clkperod_delay field in the phy_dq_timing_reg register. Each bit in this field is used to add or not 1 cycle delay to each one of the bits in the output data. In the case of the write command path, the cmd_clkperiod_delay bit in the phy_wr_rd_deskew_cmd_reg register is used for this purpose.

In the case of generating a DDR signal, the write path makes use of the CLK adder module. This module adds a configurable delay to the clk_wr or clk_wrdqs signals. These signals are used to synchronize the final data/command outputs, and controlling this delay is the mechanism that reduces the skew between data/command lines. The amount of delay that can be added to each one of the data/command lines is controlled by the phy_wr_deskew_reg register for data (4 bits per data line) and the wr_cmd_deskew_delay field in the phy_wr_rd_deskew_cmd_reg register.

In order to generate the DDR signal, you must have a data/command internal signal with a half cycle delay in the data path. The CLK adder module also produces a signal that allows control of the adding of this half cycle delay. The half_cycle_delay signal corresponds to the sampled value of the clk_wr signal by the clk_phy signal. The state of this half_cycle_delay signal can be controlled manually, or the signal can also be driven automatically by the hardware. The final half_cycle_delay signal depends on the configuration of several field registers. The following diagram shows the mechanism used to generate this signal.

Figure 160. Generation of half_cycle_delay Signal Block Diagram in Write Data Path

In the above diagram the pd_deskew, sw_half_cycle_shift, en_sw_half_cycle, and phase_bypass signals are controlled directly from register configuration. The clk_total_delay_msb signal depends on the total number of delay items in the write path for the corresponding signal. This signal corresponds to the most significant bit (bit 7th) after adding slave_delay and pd_deskew values.

The following table shows the registers and their fields used to control the signals described in this section for data and command path.

Table 228. Data and Command Path Operation
Operation	Write Data (clk_wr)	Write Command (clk_wrdqs)
Loop back enable.	`phy_gate_lpbk_ctrl_reg[lpbk_en field]`	Tied to ‘0’
Add 1 period delay.	`phy_dq_timing_reg[data_clkperiod_delay]` – 1 bit per data bit.	`phy_wr_rd_deskew_cmd_reg[cmd_clkperiod_delay]`
Delays `clk_phy` to generate `clk_wr` and `clk_wrdqs` signals.	`phy_dll_slave_ctrl_reg[clk_wr_delay]` – 8 bits	`phy_dll_slave_ctrl_reg[clk_wrdqs_delay]` – 8 bits
Add delay to DQ and CMD signals (applied over `clk_wr` and clk_wrdqs line CLK adder module).	`phy_wr_deskew_reg[wr_dqx_deskew_delay]` – 4 bit per data line.	`phy_wr_rd_deskew_cmd_reg [wr_cmd_deskew_delay]`
Enable/disable manual software half cycle. Also enable/disable automatic mode (`en_sw_half_cycle` signal).	`phy_wr_deskew_pd_ctrl_0_reg[dqx_en_sw_half_cycle]` and `phy_wr_deskew_pd_ctrl_1_reg[dqx_en_sw_half_cycle]`	`phy_wr_rd_deskew_cmd_reg[cmd_en_sw_half_cycle]`
Manual software control over `half_cycle_delay` signal.	`phy_wr_deskew_pd_ctrl_0_reg[dqx_sw_half_cycle_shift]` `phy_wr_deskew_pd_ctrl_1_reg[dqx_sw_half_cycle_shift]`	`phy_wr_rd_deskew_cmd_reg[cmd_sw_half_cycle_shift]`
Deskew value in phase detector (`pd_deskew`)	`phy_wr_deskew_pd_ctrl_0_reg[dqx_phase_detect_sel]` `phy_wr_deskew_pd_ctrl_1_reg[dqx_phase_detect_sel]`	`phy_wr_rd_deskew_cmd_reg [cmd_phase_detect_sel]`
Bypass phase detect circuit to determine `half_cycle_delay` signal.	`phy_wr_deskew_pd_ctrl_0_reg[dqx_sw_dq_phase_bypass]` `phy_wr_deskew_pd_ctrl_1_reg[dqx_sw_dq_phase_bypass]`	`phy_wr_rd_deskew_cmd_reg[cmd_sw_dq_phase_bypass]`
Operation to get `clk_total_delay_msb` bit. The `clk_total_delay_msb` corresponds to the `msb` bit of the addition of `slave_delay[7:0]` and `DQ/CMD skew[3:0]`.	`Msb of (phy_dll_slave_ctrl_reg[clk_wr_delay]) + (phy_wr_deskew_reg[wr_dqx_deskew_delay])`	`Msb of (phy_dll_slave_ctrl_reg[clk_wrdqs_delay]) + (phy_wr_rd_deskew_cmd_reg[wr_cmd_deskew_delay])`

The following figure shows an example of the data conversion by the balance module when transferring data in DDR mode. The input data high and low are synchronized with the rising edge of the clk_phy clock, while the output data transfers one bit in every clk_wr clock transition. The frequency of the clk_phy and clk_wr clocks is the same although the phase between them is ¼ of cycle.

Figure 161. Example of Clock Frequency Translation in Balance Module for DDR Data

The output of the output data selector in the data balance modules should be treated as a skew group with constraints written to minimize the skew between the eight DQ data lines as much as possible.

The output data selector component selects the appropriate signal to transmit depending on the current operation mode of the PHY. The operation mode determines the state of the input signals of this block. For reference on these signals see the Operation Modes section in this chapter.

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Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

5.5.6.5. Write Data Path