Visible to Intel only — GUID: pme1678568306028
Ixiasoft
Visible to Intel only — GUID: pme1678568306028
Ixiasoft
5.7.5.3. Target Interface
The target interface allows other initiators in the system to access the USB OTG controller’s CSRs. For testing purposes, other initiators can also access the single port RAM (SPRAM).
The target interface can read from and write to all the CSRs in the USB OTG controllers. All register accesses are 32 bits.
- Global
- Host
- Device
- Power and clock gating
Some registers are shared between host and device modes, because the controller can only be in one mode at a time. The controller generates a mode mismatch interrupt if an initiator attempts to access device registers when the controller is in host mode, or attempts to access host registers when the controller is in device mode. Writing to unimplemented registers is ignored. Reading from unimplemented registers returns indeterminate values.