Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.1.5.7. System Memory Cache

The system memory cache (SMC) allows DMI(s) to buffer cache lines and service requests without accessing next level of memory hierarchy. The SMC represents a lower-level cache in the memory hierarchy relative to those in the caching agents and NCAIU.

SMC supports a three-state cache model, a cache line may either be in an invalid state (that is, not present in the cache) or clean state (i.e. present and consistent with respect to the next level of the memory hierarchy) or dirty state (that is, present and inconsistent with respect to the next level of the memory hierarchy). SMC in general uses the native interface (CHI, ACE, ACE-Lite, AXI) allocation hint to allocate to the cache.

On Agilex™ 5, each DMI supports a 32Kbyte system memory cache (SMC) intended to enable CHI-B atomic operations.