Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
Visible to Intel only — GUID: qbc1674512315834
Ixiasoft
Visible to Intel only — GUID: qbc1674512315834
Ixiasoft
5.3.7.10. Slave DMA Programming
Follow the next sequence to access controller’s data path using slave DMA interface:
- Before the host master accesses the slave DMA interface, it needs to check if data transfer is allowed. This is done by polling the sdma_trigg bit in the intr_status (0x0110) register. Alternatively, the host can unmask the interrupt associated with sdma_trigg by setting the sdma_trigg_en bit in the intr_enable (0x0114) register. Note that if sdma_paused flag in the ctrl_status (0x0118) register is set (that is, in case of detecting unexpected transaction during earlier data transfer), the controller should not request a new SDMA transaction. In this case, software must first clear the sdma_paused flag.
- After host discovered that data transfer is allowed, it should read the sdma_size and the sdma_trd_num registers. The sdma_size (0x0440) register provides byte aligned data block size that needs to be transferred. The sdma_trd_num (0x0444) register identifies the command associated with this data transfer which allows to select valid address and direction for data transfer.
- Before starting data transmission, host must clear the sdma_trigg flag by writing 1 in the corresponding bit in intr_status (0x0110) register. After clearing this flag, the host can execute data transmission on slave DMA interface.
- If the host ignores the requirements described above and starts to transfer data when slave DMA is not ready, then the sdma_err flag is set in the intr_status (0x0110) register. If the sdma_err_en bit is set in the intr_enable (0x0114) register, then an interrupt is triggered. When the sdma_err_rsp bit is set in the dma_settings (0x043c) register, the ERROR response is returned, and if it is cleared, the OK response is returned.
- If the host sends an unsupported transaction to slave interface, the slave DMA ignores this access and both the sdma_err flag in the intr_status (0x0110) register and the sdma_paused flag in the ctrl_status (0x0118) register is set.
If a system bus error is detected after the slave DMA transfer was triggered, the Fail and bus error bits are set in the last operation status register/descriptor. Performing transactions in the wrong direction (that is, write transaction to slave DMA port in case of sending read operation command to NF device) is forbidden.