Visible to Intel only — GUID: xbp1677725643253
Ixiasoft
Visible to Intel only — GUID: xbp1677725643253
Ixiasoft
13.4.4.1. Priority Levels
Traffic on the system interconnect across the HPS implement the priorities as shown in the following table.
Priority Level | Traffic Class | Description |
---|---|---|
2 | Latency critical | Use for traffic that is least able to tolerate latency variations. Reserved for MPU and SDM in HPS. |
1 | Latency sensitive | Use for transactions with latency requirements. Initiators transferring latency sensitive traffic (for example, time-sensitive network packet processing between EMAC/TSN and FPGA) should use this priority level. |
0 | Best effort | Use for transactions without any latency requirement. Default priority of all initiators on the NoC (except MPU and SDM). All traffic should use this priority level unless the application requires better latency. |
ACE, ACE-lite, and AXI-4 defines an optional AxQOS signal to indicate the priority of a transaction. The system interconnect uses the AxQOS mapping as shown in the following table.
AxQOS[3:0] | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Priority | 0 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 |