Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.6.4.5.4. Multi-plane Commands

The NAND Flash controller in CMD DMA and PIO operation mode supports interleaved operations across multiple planes if the NAND device supports this. To perform any operation as a multiplane operation, the following should be confirmed:

  • Configure the correct number of planes in the multiplane_config (0x0434) register.
  • Set either the mpl_rd_en bit, the mpl_wr_en bit, or both in the multiplane_config (0x0434) register.
  • Set the Flash pointer in the descriptor. The block address specified must be for block in plane 0.
  • Set the number of pages in the command as a multiple of the number of planes in the device. If this setting is incorrect in CMD DMA mode the Descriptor Error bit is set in the Status field and the descriptor is dropped from execution. If this setting is incorrect in PIO mode, the Command Error bit in cmd_status (0x0014) register (for selected thread) is set and the command is dropped from execution.

For multi-plane read, program or copyback operations, the block address is incremented by 1 starting from the address defined in the Flash pointer up to the number of planes declared in mpl_pl_num field of the multiplane_config (0x0434) register and starts again from the Flash pointer block address for every sweep. The page number also is incremented after each sweep of planes present in the device until the total number of pages to transfer is completed. Refer to Layout Between Pages section for more detail about this.

For the erase operations, the controller sends the erase commands to each plane one after the other for all the available planes. This will kick off the erase operations for all the planes simultaneously in the device.

The controller can also execute multi-plane cache reads and writes on the device. If the total number of pages in the descriptor command exceeds the total number of planes while remaining a multiple of the number of planes, and if the cache_rd_en bit, the cache_wr_en bit, or both in the cache_config (0x0438) register are configured appropriately, the controller can intelligently execute multi-plane cached read or write sequences.

Refer to Configure Multi-plane and Cache Operations section for more detail about this.