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Visible to Intel only — GUID: vdf1674512132360
Ixiasoft
5.3.7.6. Interrupts Configuration
The interrupts mechanism in the NAND Flash controller uses global interrupts to enable bit to mask or unmask all available interrupts in the controller. Additionally, each interrupt in the controller has its own enable flag that allows to mask them independently. For each one of the interrupts, there are status bits that are set independently if they are masked or not. These status bits are cleared by writing a ‘1’ in that bit. The following steps need to be followed to enable the selected interrupts:
- Set the intr_en bit in the intr_enable (0x0114) register to allow propagation of the interrupts to the host,
- Individual interrupts can be enabled or disabled from the single bits also in the intr_enable (0x0114) register. The corresponding status bits can be accessed from the intr_status (0x0110) register.
- The trd_comp interrupt is a special one which is enabled by setting the INT bit of the command descriptor in CDMA work mode or the INT bit of the cmd_reg0 (0x0000) for the PIO and generic work modes. This interrupt is reported on the trd_comp field of the trd_comp_intr_status (0x0138) register. Extended status information for this interrupt is provided in descriptor Status field in the CDMA work mode or in the cmd_status (0x0014) register for the PIO and generic work mode. The thread number for which the status needs to be observed is selected by the cmd_status_ptr (0x0010) register.
Once one or more enabled interrupts have been triggered, the external interrupt line remains high until all interrupt flags are cleared by the software. If the system expects a rising edge on interrupt pin for every interrupt event, software must ensure that the appropriate interrupt flags get cleared before a new interrupt event comes, otherwise some interrupts may be missed. Especially if there is risk that two descriptors in the same chain could complete very close together (such as when using NOP command types), then it is advised to just set INT field for a single descriptor (the last one) and not all in the chain.
The interrupt status bits are not automatically cleared after given interrupt is enabled. If we do not want a previous event to trigger an interrupt, then it is advised to clear interrupt status bit corresponding to the interrupt we want to enable before enabling this.
The following tables shows the register related to interrupts in the NAND Flash controller and the status register that could provide information about an event.
Interrupt Related Registers | Description |
---|---|
trd_error_intr_en | Error state in each thread |
trd_error_intr_status | Interrupt enable after an error in a thread |
trd_comp_intr_status | Command completed in thread. Enable of interrupt using INT bit in the command flag field in descriptor (CDMA) or CMD0 register (PIO and generic) |
intr_enable | Interrupt enable for global and errors conditions detected in the NAND controller. |
intr_status | NAND Controller Error Status register |
Register | Description |
---|---|
ctrl_status | Controller internal state. Includes internal component busy state. |
trd_status | Command engine thread busy state. |
cmd_status and cmd_status_ptr | Last operation status. This is thread specific (for PIO and generic modes). For CDMA the status is provided in the Status field in the descriptor. Error Index bit can be used to identify the first index operation that caused the assertion of the Fail flag (used by CDMA and PIO). |
dma_target_error | DMA target address that causes an error. |