Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.8.3. I3C Controller Features

The HPS I3C controller supports the following different roles of devices:

  • I3C master (single master, main master)
  • I3C secondary master

The main master is a specialized master that comes up after power-on-reset, and is responsible for assigning dynamic addresses to the I3C devices. The secondary master is an I3C instance capable of both master and slave functionality. It comes up as a slave upon power-on-reset. The secondary master must get ownership of the I3C bus to become a current master before initiating any transfer to its associated slaves.

The controllers are configured to support the following:

  • Support for one I3C0 supporting master only mode
  • Support for one I3C1 supporting secondary master configurable as master or slave
  • Supports various data rates, that is, data rates up to 12.5 Mbps
  • Supports up to 2^16 (65536) write or read bytes with a single command
  • Hardware-assisted Dynamic Address Assignment (DAA) support
  • Hardware-assisted device role-switching in secondary master configuration
  • In-band interrupts supported
  • Supports data transfer to I2C slaves
  • DMA interface capability
  • Supports up to 8 slaves

The following features are not supported:

  • Dynamic re-configuration
  • Hot-Join
  • Data rates HDR, DDR
  • I2C backward-compatibility for:
    • 10-bit addressing
    • Clock stretching/synchronization
    • High-speed mode