Visible to Intel only — GUID: bxb1666810150984
Ixiasoft
Visible to Intel only — GUID: bxb1666810150984
Ixiasoft
5.9.9.1. I2C Interface Design Guidelines
GUIDELINE: Instantiate the open-drain buffer when routing I2C signals through the FPGA fabric.
When routing I2C signals through the FPGA, note that the I2C pins from the HPS to the FPGA fabric (i2c*_out_data, i2c*_out_clk) are not open-drain and are logic level inverted. Thus, to drive a logic level zero onto the I2C bus, drive the corresponding pin high. This implementation is useful as they can be used to tie to an output enable of a tri-state buffer directly. You must use the GPIO to implement the open-drain buffer.
Intel recommends that you use I/O Buffer (GPIO) IP core when you expose I2C to FPGA fabric.
The following Verilog code shows the gpio instantiation for an I2C interface implemented through the FPGA:
gpio scl_iobuf (.din(1'b0), .oe(*scl_oe), .dout(*scl_i), .pad_io(fpga_i2c_scl)); //declared bi-directional buffer for scl gpio sda_iobuf (.din(1'b0), .oe(*sda_oe), .dout(*sda_i), .pad_io(fpga_i2c_sda)); //declared bi-directional buffer for sda
GUIDELINE: Ensure that the pull-ups are added to the external SDA and SCL signals in the board design.
GUIDELINE: Ensure that the high and low clock counts are configured correctly for the speed of the I2C interface.
- SDM—125 MHz
- HPS—100 MHz