HPS cold |
POR |
- State machine immediately proceeds to “Raw POR Reset Assert” stage. Only POR is noted in STAT register.
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HPS cold |
- The reset manager extends the reset period for all the module reset outputs until all cold reset requests are removed. If a cold reset request is issued while the reset manager is removing other modules out of the reset state, the reset manager returns those modules back to the reset state.
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HPS warm reset (from SDM or watchdog) |
- Cold reset clears all other pending resets except for POR.
- Cold reset sequence continues to completion. Only cold reset is noted in the STAT register.
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Any software-initiated reset |
- This boundary condition included for completeness. May only be possible via register write from the SDM since the CPUs and debug logic are in reset.
- If the software-initiated reset request occurs before cold resets are asserted, then the cold reset clears the request, and the cold reset sequence completes. Only the source of the cold reset is noted in the STAT register. The software-initiated reset is not taken.
- If the software-initiated reset request occurs after cold resets are asserted, then the software-initiated request remains pending until the cold reset sequence is completed. The software-initiated reset request is then taken.
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HPS warm reset (from SDM or watchdog expiry) |
POR |
- State machine immediately proceeds to POR de-assertion sequence. Only POR is noted in STAT register.
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HPS cold |
- The warm reset sequence continues until the state machine reaches the “Wait for Reset Requests to De-assert Sequence.”
- The state machine goes back to the “Reset Assertion Sequence” to assert cold resets (HPS is still idle from previous warm reset request so no need to repeat idle process).
- Only the cold reset request is noted in the STAT register.
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HPS warm reset (from SDM or watchdog) |
- If the new warm reset request(s) is(are) received before warm resets are asserted, then all sources of warm reset request are noted in the STAT register. One warm reset sequence is performed.
- If the new warm reset request is received after warm resets are asserted, then the state machine goes back to the “Reset Assertion Sequence.” Only the new warm reset requests are noted in the STAT register.
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Any software-initiated reset |
- If the software-initiated reset request occurs before warm resets are asserted, then the warm reset clears the request, and the warm reset sequence completes. Only the source of warm reset is noted in the STAT register. The software-initiated reset is not taken.
- If the software-initiated reset request occurs after warm resets are asserted, then the software-initiated request remains pending until the warm reset sequence is completed. The software initiated reset request is then taken. Note: since the CPUs are in warm reset, this may only be possible via a register write from either the SDM or debugger.
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Any software-initiated bridge, CPU, or debug reset |
POR |
- State machine immediately proceeds to “POR De-assertion Sequence.” Only POR is noted in STAT register.
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Any cold or warm reset request |
- Immediately stop software-initiated reset sequence and go to “HPS Idle Sequence.”
- Software-initiated reset requests are cleared.
- Follow rules for cold and warm reset sequences given above.
- Only cold or warm reset noted in STAT register as defined above.
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Any other software-initiated reset request |
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