Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/07/2025
Public

Visible to Intel only — GUID: krg1673368048488

Ixiasoft

Document Table of Contents

5.14.4. GPIO System Integration

The figure below shows a block diagram of the GPIO interface.
Figure 254. GPIO Block Diagram
There are two GPIO module instances in the HPS and each supports 24 GPIO ports. Only Port A of the GPIO controller is configured. The following table shows the information for the GPIO interface pins.
Table 296.  GPIO Interface Pins
Pin Name Mapped to GPIO Signal Name Comments
HPS_DEDICATED_Q1 [12:1] GPIO 0 [11:0] Input / Output
HPS_DEDICATED_Q2 [12:1] GPIO 0 [23:12] Input / Output
HPS_DEDICATED_Q3 [12:1] GPIO 1 [11:0] Input / Output
HPS_DEDICATED_Q4 [12:1] GPIO 1 [23:12] Input / Output