Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.14.6. GPIO Programming Model

Debounce capability for each of the input signals can be enabled or disabled under software control by setting the corresponding bits in the gpio_debounce register accordingly. The debounce clock must be stable and operational before the debounce capability is enabled.

Under software control, the direction of the external I/O pad is controlled by a write to the gpio_swportx_ddr register. When configured as input mode, reading gpio_ext_porta reads the values on the signal of the external I/O pad. When configured as output mode, the data written to the gpio_swporta_dr register drives the output buffer of the I/O pad. The same pins are shared for both input and output modes, so they cannot be configured as input and output modes at the same time.