Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs
Visible to Intel only — GUID: pbp1676326218617
Ixiasoft
Visible to Intel only — GUID: pbp1676326218617
Ixiasoft
11.5.4. FPGA-to-SDRAM Bridge
F2SDRAM bridge allows logic in the fabric to perform non-coherent access to SDRAM. The access supports 256/128/64-bit AXI-4 interface.
The following figure shows the F2SDRAM block diagram.
The following table lists the signals for the F2SDRAM bridge.
Name | Direction | Description |
---|---|---|
f2sdram_axi_clock | Input | Clock from a single source in FPGA |
f2sdram_axi_reset | Input | Async active high reset to the bridge |
F2SDRAM_port_size_config[2:0] | Input | [2]: reserved [1:0]: Port width selection:
|
The following table shows the properties of the F2SDRAM bridge.
Bridge Property | Value |
---|---|
Protocol | AXI |
Clock | f2sdram_axi_clock (from Fabric) |
Data Width | 64/128/256 |
Address Width | 40 |
ID Width | 5 |
A*Region Width | 0 |
A*Len Width | 9/8/7 ( 64/128/256 ) |
A*QoS Width | 4 |
FIXED Burst | No |
Exclusive Support | Yes |
Min Narrow Burst Size | 1 byte |
Max Wrap Burst length | 16 |
nPendingTrans (Issuance/Acceptance) | 16 |
nPendingOrderID | 16 |
Read Interleaving Yes | Yes |
Ready Latency requirement Yes | Yes |