Visible to Intel only — GUID: nbs1676413977500
Ixiasoft
Visible to Intel only — GUID: nbs1676413977500
Ixiasoft
11.8.3.3. FPGA-to-HPS CCU to Memory (Cache-Allocate)
The interface from the FPGA to the HPS CCU is ACE-Lite. These transactions go through the CCU, but can be cached or not cached, based on AxCACHE parameters. Transactions can be privileged or non privileged depending on memory allocation.
If you do a cache allocate transaction, the CCU maintains coherency and allocates in the cache. This is useful when you want to maintain coherency and keep data available in the system with minimal latency, so the masters avoid traversing to the external memory for each transaction.
Reads are processed as follows:
- On cache hits, read data is returned by the cache.
- On cache misses, read data is returned from main memory and allocated (stored) in cache.
The following table shows the read data attribute list.
Attribute | Value | Note |
---|---|---|
ARDOMAIN[1:0] | ‘b01 | Inner sharable |
ARBAR[1:0] | ‘b00 | Normal access, respecting barriers |
ARSNOOP[3:0] | ‘b0000 | ReadOnce |
ARCACHE[3:0] | ‘b1111 | Write-back read-allocate |
AxUSER[7:0] | ‘b00000100 | 0x04 = CCU |
AxPROT[2:0] | ‘b001 | Data access. Secure access. Privileged access. |
AxLEN[7:0] |
- | The burst length for:
|
AxSIZE[2:0] | - | The number of bytes in a transfer must be equal to the data bus width. |
AxBURST[1:0] | ‘b01 or ‘b10 | Must be INCR(‘b01) or WRAP(‘b10) |
AxLOCK[1:0] | ‘b00 | Must be normal access |
AxQOS | - | Do not care |
Writes are processed as follows:
- On cache hits, write data is stored in cache.
- On cache misses, write data is allocated (stored) in cache.
The following table shows the write data attribute list.
Attribute | Value | Note |
---|---|---|
AWDOMAIN[1:0] | ‘b01 | Inner sharable |
AWBAR[1:0] | ‘b00 | Normal access, respecting barriers |
AWSNOOP[2:0] | ‘b000 | WriteUnique (could be ‘b001 for WriteLineUnique) |
AWCACHE[3:0] | ‘b1111 | Write-back write-allocate |
AxUSER[7:0] | ‘b00000100 | 0x04 = CCU |
AxPROT[2:0] | ‘b001 | Data access. Secure access. Privileged access. |
AxLEN[7:0] |
- | The burst length for:
|
AxSIZE[2:0] | - | The number of bytes in a transfer must be equal to the data bus width. |
AxBURST[1:0] | ‘b01 or ‘b10 | Must be INCR(‘b01) or WRAP(‘b10) |
AxLOCK[1:0] | ‘b00 | Must be normal access |
AxQOS | - | Do not care |