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Ixiasoft
Visible to Intel only — GUID: mee1674512361525
Ixiasoft
5.3.7.11. Data Pre-Fetching Mechanism
In normal NAND operations, the NAND Flash controller pauses a transaction on system bus when the amount of data is not enough for the controller to process this. Some reasons of this may be that the NAND Flash device is too slow, or perhaps the BCH calculation takes long time. In order to overcome this problem, the data pre-fetching mechanism splits transactions into smaller packages. This mechanism is used by MDMA and SDMA data transfers.
For read transactions, specified number of data (fifo_trigg_lvl) is first buffered in internal Tx FIFO before invoking transaction of full package (dma_package_size) on the system interface. This minimizes the number of pauses during data transfer on the system interface as the DMA module has sufficient data buffered to handle transaction.
For write operations, the transaction on the system interface is invoked for a single package (dma_package_size) only when there is a specified number (fifo_trigg_lvl) of free space in internal Tx FIFO buffer. This allows us to minimize the window time in which the system bus is used.
In order to enable data pre-fetching mechanism, the host must program the fifo_trigg_level (0x0454) register. Both fields of the register are encoded on a number of 64-bit data words. The value to be written to the register can be calculated as follows:
fifo_trigg_lvl = (number of data byte to store in fifo before transmitting them)/8
dma_package_size = (number of data bytes to transfer in a single package)/8
Exact value of these fields depends on application. For example, if package size should be 1KB and whole package should be buffered before starting transaction:
dma_package_size = fifo_trigg_lvl = (1024/8) = 128
The value of the fifo_trigg_lvl should not be greater than TX FIFO depth (128 words), otherwise the behavior of the controller may be unpredictable.
Setting value of the fifo_trigg_lvl to zero results in disabling the data pre-fetching mechanism.