Visible to Intel only — GUID: abz1675368471554
Ixiasoft
Visible to Intel only — GUID: abz1675368471554
Ixiasoft
4.3.7.4. Allocating the Event Queue
The SMMU uses the Event queue to signal events. Software must allocate memory for event queue.
- Allocate memory for the Event queue.
- Program the SMMU_IDR1.EVENTQS to maximum number of Event Queue entries.
- Set the Event Queue base address by writing SMMU_EVENTQ_BASE.ADDR register; write the SMMU_EVENTQ_BASE.LOG2SIZE as queue size as log2(entries); LOGSIZE must be less than or equal to EVENTQS. The Event queue related registers are given in the following table.
- Set the Event queue read index in SMMU_EVENTQ_CONS.RD and queue write index in SMMU_EVENTQ_PROD.WR to 0.
- Program the SMMU_CR0.EVENTQEN as 1 to enable event queue processing.
Register Name |
Address |
Description |
---|---|---|
SMMU_EVENTQ_BASE_LO_ADDR |
0xA0 |
Non-secure Event Queue Base Address Low |
SMMU_EVENTQ_BASE_HI_ADDR |
0xA4 |
Non-secure Event Queue Base Address High |
SMMU_S_EVENTQ_BASE_LO_ADDR |
0x80A0 |
Secure Event Queue Base Address Low |
SMMU_S_EVENTQ_BASE_HI_ADDR |
0x80A4 |
Secure Event Queue Base Address High |
SMMU_EVENTQ_PROD_ADDR |
0x100A8 |
Non-secure Event Queue Producer Address |
SMMU_S_EVENTQ_PROD_ADDR |
0x80A8 |
Secure Command Event Producer Address |
SMMU_EVENTQ_CONS_ADDR |
0x100AC |
Non-secure Event Queue Consumer Address |
SMMU_S_EVENTQ_CONS_ADDR |
0x80AC |
Secure Command Queue Consumer Address |
The actual commands are processed as part of Queue Table Walk (QTW) over ACE-Lite+DVM interface.