GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Error Handling 3.5. Link Debugging Sequence
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

3.5. Link Debugging Sequence

The GTS Serial Lite IV IP provides a link debugging sequence for TX and RX that you can use when debugging your design.
Figure 9. TX Link Debugging Flowchart
Table 10.  TX Link Debugging Signals
Signal Location Description
tx_link_up Top-level TX signal The IP asserts this signal to indicate that the initialization sequence is complete and the IP is ready to transmit the data.
tx_pll_locked Top-level PHY signal This active-high signal indicates that the transceivers are locked to the reference clock.
Figure 10. RX Link Debugging Flowchart
Table 11.  RX Link Debugging Signals
Signal Location Description
rx_link_up Top-level RX signal The IP asserts this signal to indicate that the initialization sequence is complete, and the IP is ready to receive data.
phy_rx_pcs_ready[(n*2)-1:0] Top-level PHY signal The IP asserts this signal when RX datapath is ready to receive data.
phy_rx_block_lock[(n*2)-1:0] Top-level PHY signal The IP asserts this signal to indicate the 66b block alignment has completed for the lanes.
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