Visible to Intel only — GUID: vrm1696958215943
Ixiasoft
Visible to Intel only — GUID: vrm1696958215943
Ixiasoft
7.6. Transmit Flow Control Credit Interface
The link partner's receive buffer space information is provided to application through the Transmit Flow Control Credit Interface. The credits are advertised as the limit value as specified in the PCIe* specification. Apart from the AXI-Stream ready-valid handshake, the application transmits packet only when link partner receive buffer has enough space to accept the TLP. The interface provides posted, non-posted, completion data, and header credit information. One data credit is equal to four dwords (DWs) and one header credit is equal to the max size header plus optional digest field.
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
p<n>_ss_app_st_txcrdt_tvalid | Output | p<n>_axi_st_clk | p<n>_ss_app_st_txcrdt_tvalid indicates that the credit information on p<n>_ss_app_st_txcrdt_tdata is valid. |
p<n>_ss_app_st_txcrdt_tdata[18:0] | Output | p<n>_axi_st_clk | Carries credit limit information and type of credit.
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The following figure shows the credit limit update on the Transmit Flow Control Credit Interface. The credit limit is first initialized to 0 for all the credit types. In the example below, updated credit limit is output from cycle 9 to cycle 14. When the HOST returns the credit after receiving the packet, credit limit is incremented by the number of credits returned. At cycle 16, one posted header credit is returned; at cycle 19, four posted data credit is returned.