GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 8/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters for E-Series FPGA 6. IP Parameters for D-Series FPGAs 7. Interfaces and Signals 8. Registers 9. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Precision Time Measurement (PTM) 4.11. Single Root I/O Virtualization (SR-IOV) 4.12. Transaction Layer Packet (TLP) Bypass Mode 4.13. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.11. Single Root I/O Virtualization (SR-IOV) x
4.11.1. SR-IOV Implementation
4.12. Transaction Layer Packet (TLP) Bypass Mode x
4.12.1. AXI-Lite Usage for TLP Bypass Mode 4.12.2. Configuration TLP 4.12.3. Transmit Interface 4.12.4. Receive Interface 4.12.5. Malformed TLP 4.12.6. ECRC
5. IP Parameters for E-Series FPGA x
5.1. PCIe* Interfaces 0 Settings 5.2. AXI Interfaces 0 Settings 5.3. PCIe* 0 Settings
5.3. PCIe* 0 Settings x
5.3.1. PCIe* 0 Base Address Registers 5.3.2. PCIe* 0 Device Identification Registers 5.3.3. PCIe* 0 PCI Express* / PCI Capabilities
6. IP Parameters for D-Series FPGAs x
6.1. PCIe Interface 0 Settings 6.2. AXI Interfaces 0 Settings 6.3. PCIe0/PCIe1 Settings
6.3. PCIe0/PCIe1 Settings x
6.3.1. PCIe0/PCIe1 Base Address Registers 6.3.2. PCIe0/PCIe1 Device Identification Registers 6.3.3. PCIe0/PCIe1 PCI Express / PCI Capabilities
7. Interfaces and Signals x
7.1. Overview 7.2. Clocks and Resets 7.3. AXI4-Stream Interfaces 7.4. Configuration Intercept Interface 7.5. Control Shadow Interface 7.6. Transmit Flow Control Credit Interface 7.7. Completion Timeout Interface 7.8. Control and Status Register Responder Interface 7.9. Function Level Reset Interface 7.10. TLP Bypass Error Reporting Interface 7.11. VF Error Flag Interface 7.12. Precision Time Measurement (PTM) Interface 7.13. Serial Data Signals 7.14. Miscellaneous Signals
7.2. Clocks and Resets x
7.2.1. Interface Clock Signals 7.2.2. Interface Reset Signals
7.3. AXI4-Stream Interfaces x
7.3.1. AXI4-Stream Receive (RX) Interface 7.3.2. AXI4-Stream Transmit (TX) Interface
7.4. Configuration Intercept Interface x
7.4.1. Configuration Intercept Request Interface 7.4.2. Configuration Intercept Response Interface
7.9. Function Level Reset Interface x
7.9.1. Function Level Reset Received Interface 7.9.2. Function Level Reset Completion Interface
8. Registers x
8.1. Register Address Map 8.2. PCI Express* Configuration Space 8.3. HIP Port and Status Registers 8.4. Soft Register Address Map 8.5. Indirect Register Access 8.6. Virtual Function (VF) PCI Express* Configuration Space 8.7. Intel-Defined VSEC Capability Register
8.2. PCI Express* Configuration Space x
8.2.1. PCI Express* Configuration Header Registers 8.2.2. PCI Express* Capability Structures 8.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
8.3. HIP Port and Status Registers x
8.3.1. Root Port Interrupt Registers 8.3.2. PTM Registers
8.4. Soft Register Address Map x
8.4.1. Control Registers 8.4.2. Debug Registers 8.4.3. Performance Monitor Registers
8.6. Virtual Function (VF) PCI Express* Configuration Space x
8.6.1. VF PCI-Compatible Configuration Space Header Type0 8.6.2. VF PCI Express* Capability Structure 8.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 8.6.4. VF Alternative Routing ID (ARI) Capability Structure 8.6.5. VF TLP Processing Hints (TPH) Capability Structure 8.6.6. VF Address Translation Services (ATS) Capability Structure 8.6.7. VF Access Control Services (ACS) Capability Structure
8.6.1. VF PCI-Compatible Configuration Space Header Type0 x
8.6.1.1. Vendor ID and Device ID Registers 8.6.1.2. Command Registers 8.6.1.3. Status Registers 8.6.1.4. Revision ID and Class Code Register 8.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 8.6.1.6. Subsystem Vendor ID and Subsystem ID Register 8.6.1.7. Capabilities Pointer
8.6.2. VF PCI Express* Capability Structure x
8.6.2.1. PCI Express* Capability List Register 8.6.2.2. PCI Express* Device Capabilities Register 8.6.2.3. PCI Express* Device Control and Status Register 8.6.2.4. Link Capabilities Register 8.6.2.5. Link Control and Status Register 8.6.2.6. PCI Express* Device Capabilities 2 Register 8.6.2.7. PCI Express* Device Control and Status 2 Register 8.6.2.8. Link Capabilities 2 Register 8.6.2.9. Link Control and Status 2 Register
8.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
8.6.3.1. MSI-X Control Register 8.6.3.2. MSI-X Table Offset Register 8.6.3.3. MSI-X Pending Bit Array Register
8.6.4. VF Alternative Routing ID (ARI) Capability Structure x
8.6.4.1. ARI Enhanced Capability Header Register 8.6.4.2. ARI Capability and Control Registers
8.6.5. VF TLP Processing Hints (TPH) Capability Structure x
8.6.5.1. TPH Requester Enhanced Capability Header 8.6.5.2. TPH Requester Capability Register 8.6.5.3. TPH Requester Control Register
8.6.6. VF Address Translation Services (ATS) Capability Structure x
8.6.6.1. ATS Enhanced Capability Header 8.6.6.2. ATS Capability Register and Control Register
8.6.7. VF Access Control Services (ACS) Capability Structure x
8.6.7.1. ACS Extended Capability Header 8.6.7.2. ACS Capability and Control Register 8.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters for E-Series FPGA
6. IP Parameters for D-Series FPGAs
7. Interfaces and Signals
8. Registers
9. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation

4.12.4. Receive Interface

All TLPs received by the IP are transmitted to the application through the RX streaming interface (except Malformed TLPs). All PCIe* protocol errors leading up to designating a TLP as a good packet or not are detected by the Hard IP and communicated to user logic to take appropriate action in terms of error logging and escalation. The IP does not generate any error message internally since this is the responsibility of the user logic.

Table 24.  RX Packets Forwarded in EP TLP Bypass Mode
TLP Type Routing Direction TLP Corruption Forwarded to AXI-Stream Interface
ASSERT/DEASSERT INTx Local Upstream None No
Ecrc_err No
Malformed No
VENDOR_MESSAGE_0/1 Route_to_RC Upstream None

No (VENDOR0)

Yes (VENDOR1)
Poisoned

No (VENDOR0)

Yes (VENDOR1)
Ecrc_err Yes
Malformed No
VENDOR_MESSAGE_0/1 Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
VENDOR_MESSAGE_0/1 Broadcast Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
VENDOR_MESSAGE_0/1 Local Both None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
PM_ACTIVE_STATE_NAK Local Downstream None Yes
Ecrc_err Yes
Malformed No
PM_PME Route_to_RC Upstream None No
Ecrc_err Yes
Malformed No
PME_TURN_OFF Broadcast Downstream None Yes
Ecrc_err Yes
Malformed No
PME_TO_ACK Gather Upstream None No
Ecrc_err Yes
Malformed No
ERR_COR Route_to_RC Upstream None No
Ecrc_err Yes
Malformed No
ERR_NONFATAL Route_to_RC Upstream None No
Ecrc_err Yes
Malformed No
ERR_FATAL Route_to_RC Upstream None No
Ecrc_err Yes
Malformed No
UNLOCK Broadcast Downstream None Yes
Ecrc_err Yes
Malformed No
SET_SLOT_POWER_LIMIT Local Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
LN_MESSAGE Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
LN_MESSAGE Broadcast Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
DRS_MESSAGE Local Upstream None Yes
Ecrc_err Yes
Malformed No
FRS_MESSAGE Route_to_RC Upstream None Yes
Ecrc_err Yes
Malformed No
HIERARCHY_ID_MSG Broadcast Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_ON Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_BLINK Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_OFF Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_IND_ON Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_IND_BLINK Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_IND_OFF Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_BT_PRESS Local Upstream None Yes
Ecrc_err Yes
Malformed No
LTR_MESSAGE Local Upstream None No
Poisoned No
Ecrc_err Yes
Malformed No
OBFF_MESSAGE Local Downstream None No
Poisoned No
Ecrc_err Yes
Malformed No
PTM_REQUEST Local Upstream None No
Ecrc_err Yes
Malformed No
PTM_RESPONSE Local Downstream None No
Poisoned No
Ecrc_err Yes
Malformed No
PTM_RESPONSE_D Local Downstream None No
Poisoned No
Ecrc_err Yes
Malformed No
INVALIDATE_REQUEST Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
INVALIDATE_COMPLETION Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
CFG_WR_0 Route_by_ID Downstream None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
CFG_WR_1 Route_by_ID Downstream None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
CFG_RD_0 Route_by_ID Downstream None Yes
ID_mismatch Yes
Ecrc_err Yes
Malformed No
CFG_RD_1 Route_by_ID Downstream None Yes
ID_mismatch Yes
Ecrc_err Yes
Malformed No
IO_WR Address Downstream None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
IO_RD Address Downstream None Yes
Addr_mismatch Yes
Ecrc_err Yes
Malformed No
MEM_WR_32/64 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
MEM_RD_32/64 Address Both None Yes
Addr_mismatch Yes
Ecrc_err Yes
Malformed No
MEM_RD_LK_32/64 Address Both None Yes
Addr_mismatch Yes
Ecrc_err Yes
Malformed No
ATOMIC_FETCH_ADD_32/64 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
ATOMIC_SWAP_32/64 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
ATOMIC_CAS_32/64/128 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed

32/64: No

128: No stimulus
CPL Route_by_ID Both None Yes
ID_mismatch Yes
LUT_mismatch Yes
Ecrc_err Yes
Malformed No
CA_status Yes
UR_status Yes
CRS_status Yes
CPLD Route_by_ID Both None Yes
ID_mismatch Yes
LUT_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
Table 25.  RX Packets Forwarded in RC TLP Bypass Mode
TLP Type Routing Direction TLP Corruption Forwarded to AXI-Stream Interface
ASSERT/DEASSERT INTx Local Upstream None Yes
Ecrc_err Yes
Malformed No
VENDOR_MESSAGE_0/1 Route_to_RC Upstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
VENDOR_MESSAGE_0/1 Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
VENDOR_MESSAGE_0/1 Broadcast Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
VENDOR_MESSAGE_0/1 Local Both None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
PM_ACTIVE_STATE_NAK Local Downstream None Yes
Ecrc_err Yes
Malformed No
PM_PME Route_to_RC Upstream None Yes
Ecrc_err Yes
Malformed No
PME_TURN_OFF Broadcast Downstream None Yes
Ecrc_err Yes
Malformed No
PME_TO_ACK Gather Upstream None Yes
Ecrc_err Yes
Malformed No
ERR_COR Route_to_RC Upstream None Yes
Ecrc_err Yes
Malformed No
ERR_NONFATAL Route_to_RC Upstream None Yes
Ecrc_err Yes
Malformed No
ERR_FATAL Route_to_RC Upstream None Yes
Ecrc_err Yes
Malformed No
UNLOCK Broadcast Downstream None Yes
Ecrc_err Yes
Malformed No
SET_SLOT_POWER_LIMIT Local Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
LN_MESSAGE Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
LN_MESSAGE Broadcast Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
DRS_MESSAGE Local Upstream None Yes
Ecrc_err Yes
Malformed No
FRS_MESSAGE Route_to_RC Upstream None Yes
Ecrc_err Yes
Malformed No
HIERARCHY_ID_MSG Broadcast Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_ON Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_BLINK Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_OFF Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_IND_ON Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_IND_BLINK Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_IND_OFF Local Downstream None Yes
Ecrc_err Yes
Malformed No
IGNORED_MSG_ATT_BT_PRESS Local Upstream None Yes
Ecrc_err Yes
Malformed No
LTR_MESSAGE Local Upstream None Yes
Ecrc_err Yes
Malformed No
OBFF_MESSAGE Local Downstream None Yes
Ecrc_err Yes
Malformed No
PTM_REQUEST Local Upstream None Yes
Ecrc_err Yes
Malformed No
PTM_RESPONSE Local Downstream None Yes
Ecrc_err Yes
Malformed No
PTM_RESPONSE_D Local Downstream None Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
INVALIDATE_REQUEST Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
INVALIDATE_COMPLETION Route_by_ID Both None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
CFG_WR_0 Route_by_ID Downstream None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
CFG_WR_1 Route_by_ID Downstream None Yes
ID_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
CFG_RD_0 Route_by_ID Downstream None Yes
ID_mismatch Yes
Ecrc_err Yes
Malformed No
CFG_RD_1 Route_by_ID Downstream None Yes
ID_mismatch Yes
Ecrc_err Yes
Malformed No
IO_WR Address Downstream None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
IO_RD Address Downstream None Yes
Addr_mismatch Yes
Ecrc_err Yes
Malformed No
MEM_WR_32/64 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
MEM_RD_32/64 Address Both None Yes
Addr_mismatch Yes
Ecrc_err Yes
Malformed No
ATOMIC_FETCH_ADD_32/64 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
ATOMIC_SWAP_32/64 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
ATOMIC_CAS_32/64/128 Address Both None Yes
Addr_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
CPL Route_by_ID Both None Yes
ID_mismatch Yes
LUT_mismatch Yes
Ecrc_err Yes
Malformed No
CA_status Yes
UR_status Yes
CRS_status Yes
CPLD Route_by_ID Both None Yes
ID_mismatch Yes
LUT_mismatch Yes
Poisoned Yes
Ecrc_err Yes
Malformed No
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