GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

A.2.4.2.3. P0 Configuration Space

This tab allows you to read the configuration space registers for that port. There is a separate tab with the configuration space for each port.

Figure 77. Example of Agilex™ 5 PCIe Configuration Settings