Visible to Intel only — GUID: zin1696475676563
Ixiasoft
Visible to Intel only — GUID: zin1696475676563
Ixiasoft
4.5.2. Message Signaled Interrupts (MSI)
The user application generates MSI, which are single-Dword memory write TLPs to implement interrupts. This interrupt mechanism conserves pins because it does not use separate wires for interrupts. In addition, the single Dword provides flexibility for the data presented in the interrupt message. The Configuration Space stores the MSI Capability structure and is programmed using Configuration Space accesses.
MSI interrupts are signaled on the PCI Express* link using a single dword Memory Write TLP. The user application issues an MSI request (MWr) through the AXI-Stream interface and updates the configuration space register using the axi_lite interface. For more details on the MSI Capability Structure, refer to the PCI Express* Configuration Space section.
The Mask Bits register and Pending Bits register are 32 bits in length each, with each potential interrupt message having its own mask bit and pending bit. If bit[0] of the Mask Bits register is set, interrupt message 0 is masked. When an interrupt message is masked, the MSI for that vector cannot be sent. If software clears the mask bit and the corresponding pending bit is set, the function must send the MSI request at that time. You should obtain the necessary MSI information (such as the message address and data) from the Control Shadow Interface to create the MWr TLP in the format shown in the following figure to be sent through the AXI-Stream interface.
By accessing configuration space register (CSR), “MSI PENDING CTRL” and “MSI PENDING” from application, the GTS AXI Streaming IP converts the CSR access to MSI Pending Interrupt Message to be sent over to PCIe* HIP.
Your application needs to write “0x1” to “MSI PENDING CTRL” through the AXI4-Lite Control and Status Register Responder interface to cause an update to the MSI Pending Bits based on MSI PENDING value. The request is expected to be ignored if bit is already set while the bit 0 of “MSI PENDING CTRL” is expected to be cleared when the request is completed. Hence, your application may need to read back the written register value to check if the request has been attended.
The following table describes three example implementations. The first example allocates all 32 MSI messages. The second and third examples only allocate four interrupts.
MSI | Allocated | ||
---|---|---|---|
32 | 4 | 4 | |
System Error | 31 | 3 | 3 |
Hot Plug and Power Management Event | 30 | 2 | 3 |
Application Layer | 29:0 | 1:0 | 2:0 |
The MSI interrupts generated for Hot Plug, Power Management Events, and System Errors always use Traffic Class 0. MSI interrupts generated by the Application Layer can use any Traffic Class. For example, a DMA that generates an MSI at the end of a transmission can use the same traffic control as was used to transfer data.
The following figure illustrates a possible implementation of the Interrupt Handler Module with a per vector enable bit in the Application Layer. Alternatively, the Application Layer can implement a global interrupt enable instead of this per vector MSI.