GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 4/07/2025
Public

Visible to Intel only — GUID: noq1711331268180

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Document Table of Contents

2.6. IP Core and Design Example Support Levels

Table 11.   GTS AXI Streaming IP Support Matrix for Agilex™ 5 Device

Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported

Configuration IP Support Design Example Support
EP RP BP EP RP BP
PCIe* 4.0 x8 512-bit S,C,T,H S,C,T,H S,C,T,H N/A N/A N/A
PCIe* 4.0 x4 256-bit S,C,T,H S,C,T,H S,C,T,H S,C,T N/A N/A
PCIe* 4.0 x2 128-bit S,C,T,H S,C,T,H S,C,T,H N/A N/A N/A
PCIe* 4.0 x1 128-bit S,C,T,H S,C,T,H S,C,T,H N/A N/A N/A
PCIe* 3.0 x8 256-bit S,C,T,H S,C,T,H S,C,T,H N/A N/A N/A
PCIe* 3.0 x4 128-bit S,C,T,H S,C,T,H S,C,T,H S,C,T,H N/A N/A
PCIe* 3.0 x2 128-bit S,C,T,H S,C,T,H S,C,T,H N/A N/A N/A
PCIe* 3.0 x1 128-bit S,C,T,H S,C,T,H S,C,T,H S,C,T,H N/A N/A
Table 12.   GTS AXI Streaming IP Support Matrix for Agilex™ 3 Device

Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported

Configuration IP Support Design Example Support
EP RP EP RP
PCIe* 3.0 x4 128-bit S,C,T S,C,T S,C,T N/A
PCIe* 3.0 x2 128-bit S,C,T S,C,T N/A N/A
PCIe* 3.0 x1 128-bit S,C,T S,C,T S,C,T N/A