GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
5. IP Parameters x
5.1. System Settings 5.2. PCIe0/PCIe1 5.3. Diagnostics
5.2. PCIe0/PCIe1 x
5.2.1. Interfaces Port 0/Interfaces Port 1 5.2.2. PCIe0/PCIe1 Settings
5.2.1. Interfaces Port 0/Interfaces Port 1 x
5.2.1.1. AXI Interfaces 0/AXI Interface 1 Settings
5.2.2. PCIe0/PCIe1 Settings x
5.2.2.1. PCIe0/PCIe1 Base Address Registers 5.2.2.2. PCIe0/PCIe1 Device Identification Registers 5.2.2.3. PCIe0/PCIe1 PCI Express / PCI Capabilities
5.2.2.3. PCIe0/PCIe1 PCI Express / PCI Capabilities x
5.2.2.3.1. PCIe0/PCIe1 Device 5.2.2.3.2. PCIe0/PCIe1 Link 5.2.2.3.3. PCIe0/PCIe1 Slot 5.2.2.3.4. PCIe0/PCIe1 Legacy Interrupt Pin Register 5.2.2.3.5. PCIe0/PCIe1 PTM 5.2.2.3.6. PCIe0/PCIe1 LTR 5.2.2.3.7. PCIe0/PCIe1 MSI 5.2.2.3.8. PCIe0/PCIe1 MSI-X 5.2.2.3.9. PCIe0/PCIe1 PASID 5.2.2.3.10. PCIe0/PCIe1 DEV SER 5.2.2.3.11. PCIe0/PCIe1 PRS 5.2.2.3.12. PCIe0/PCIe1 Power Management 5.2.2.3.13. PCIe0/PCIe1 VSEC 5.2.2.3.14. PCIe0/PCIe1 ATS 5.2.2.3.15. PCIe0/PCIe1 TPH 5.2.2.3.16. PCIe0/PCIe1 ACS 5.2.2.3.17. PCIe0/PCIe1 Hot-Plug 5.2.2.3.18. PCIe0/PCIe1 VIRTIO
5.2.2.3.18. PCIe0/PCIe1 VIRTIO x
5.2.2.3.18.1. PCIe0/PCIe1 PF<n> VIRTIO STRUCTURES
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals Cold Reset Entry and Exit Sequence Warm Reset Entry and Exit Sequence User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

6.2.2. Interface Reset Signals

Table 58.  Interface Reset Signalsn = 0 or 1, p0 = port 0, and p1 = port 1
Note: Port 1 is only available in D-Series FPGAs
EP = Endpoint, RP = Root Port, BP = TLP Bypass
Signal Name Direction Port Mode Description
p<n>_subsystem_cold_rst_n Input EP/RP/BP

GTS AXI Streaming IP global reset.

Active low signal. Resets sticky register bits.

Can be implemented as synchronous or asynchronous reset.

p<n>_subsystem_warm_rst_n

Input EP/RP/BP

GTS AXI Streaming IP warm reset.

Active low signal. Does not reset sticky register bits.

Can be implemented as synchronous or asynchronous reset.
p<n>_subsystem_cold_rst_ack_n Output EP/RP/BP

Indicates that a cold reset action is completed by the GTS AXI Streaming IP.

Asynchronous handshake signal
p<n>_subsystem_warm_rst_ack_n Output EP/RP/BP

Indicates that a warm reset action is completed by the GTS AXI Streaming IP.

Asynchronous handshake signal.
p<n>_axi_st_areset_n Input EP/RP/BP

Used to reset the AXI-Stream datapath interface. Active low reset signal.

The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of p<n>_axi_st_clk.

p<n>_axi_lite_areset_n Input EP/RP/BP

. Used to reset the AXI4-Lite Control and Status Register Responder interface. Active low reset signal.

The reset signal can be asserted asynchronously, but deassertion must be synchronous after the rising edge of p<n>_axi_lite_clk.

p<n>_subsystem_rst_req Input EP/RP/BP

Reset entry indication from user reset control logic.

The GTS AXI Streaming IP queries the blocks in design upon receiving this request and sends an acknowledgment back when the block is ready for reset entry.

Asynchronous handshake signal.
p<n>_subsystem_rst_rdy Output EP/RP/BP

Ready signal for the reset entry indication from the GTS AXI Streaming IP to the user reset control logic.

Asynchronous handshake signal.
p<n>_initiate_warmrst_req Output EP/RP/BP

Warm Reset entry required indication from the IP core to user reset control logic.

The initiator block cannot issue new reset entry request until previous reset sequence (entire reset operation) is completed.

Asynchronous handshake signal.
p<n>_initiate_rst_req_rdy Input EP/RP/BP

Indicates user reset control logic has accepted initiation request and starts issuing resets.

Asynchronous handshake signal.
p0_pin_perst_n_i

p0_pin_perst_n_1_i

p1_pin_perst_n_i

Input EP/RP/BP

This is an active low input for the PERST# function defined by the PCIe* specification. Connect PERST# to either one of the reset pins.

You must assign a weak pull down to this pin in the Quartus® Prime software setting file. Example:

set_instance_assignment -name WEAK_PULL_DOWN ON -to p0_pin_perst_n_i
p<n>_pin_perst_n Output EP/RP/BP This is the PERST# indication for the HIP.
p<n>_reset_status_n Output EP/RP/BP

Active low signal. When low, it indicates the HIP is in reset state.

The application logic can use this signal to drive its reset network.

Synchronous to coreclkout_hip of HIP.

ninit_done Input EP/RP/BP

A "1" on this active low signal indicates that the FPGA device is not yet fully configured.

A "0" indicates the device has been configured and is in normal operating mode.
Note: You must implement the user reset sequencer in application user logic and follow the assertion and deassertion sequence for graceful entry and exit for each of the resets (cold, warm, etc.).

The following table indicates the signals or blocks used for each type of reset.

Table 59.  Signals or Blocks Used for Reset Type
Reset Type Signals/Blocks Under Reset
Cold Reset
  • subsystem_cold_rst_n and subsystem_warm_rst_n are asserted.
  • p0_axi_st_areset_n and p0_axi_lite_areset_n are asserted.
  • HIP undergoes reset.
Warm Reset (e.g., LTSSM Hot reset)
  • subsystem_warm_rst_n is asserted.
  • p0_axi_st_areset_n and p0_axi_lite_areset_n are asserted.
  • HIP undergoes reset too.
The expected reset isolation requirements for reset domain crossings are shown in the following table:
Table 60.  Reset Isolation Requirement for Reset Domain Crossings
  • No: No reset isolation required for Column->Row Reset Domain Crossing
  • Yes: Reset isolation required for Column->Row Reset Domain Crossing
  • N/A: Not applicable since same Reset Domain Crossing
Column: Source

Row: Destination

 Cold Reset HIP Reset Warm Reset AXI-Stream Reset AXI-Lite Reset
Cold Reset N/A No Yes No No
HIP Reset No N/A No No No
Warm Reset No No N/A No No
AXI-Stream Reset No No No N/A No
AXI-Lite Reset No No No No N/A
Note: In endpoint mode, the warm reset can be asserted without cold reset in scenarios such as LTSSM hot reset.

Cold Reset Entry and Exit Sequence

Following is the Cold Reset entry.
  1. Cold Reset is initiated by the deassertion of HIP input signal p<n>_pin_perst_n_i.
  2. HIP asserts pld_link_reset_req to the GTS AXI Streaming IP.
  3. The GTS AXI Streaming IP notifies the user reset controller by asserting p<n>_initiate_warmrst_req.
  4. The user reset controller asserts p0_subsystem_rst_req.
  5. The GTS AXI Streaming IP sequences its internal blocks for reset entry. When the internal blocks are ready for reset, the GTS AXI Streaming IP asserts p<n>_subsystem_rst_rdy to the user reset controller.
  6. The user reset controller acknowledges to the GTS AXI Streaming IP that it is ready for reset by asserting p<n>_initiate_rst_req_rdy.
  7. The GTS AXI Streaming IP then asserts pld_warm_rst_rdy to HIP.
  8. HIP asserts p<n>_reset_status_n indicating the application logic needs to be in reset.
  9. User reset controller asserts p<n>_subsystem_cold_rst_n, p<n>_subsystem_warm_rst_n, p<n>_axi_st_areset_n, and p<n>_axi_lite_areset_n.
Figure 40. Cold Reset Entry and Exit Sequence Timing Diagram

Warm Reset Entry and Exit Sequence

Warm Reset is initiated by the assertion of a HIP event, for example, hot reset. Following is the Warm Reset entry sequence.
  1. HIP asserts pld_link_reset_req to the GTS AXI Streaming IP.
  2. The GTS AXI Streaming IP notifies the user reset controller by asserting p<n>_initiate_warmrst_req.
  3. The user reset controller then asserts p<n>_subsystem_rst_req.
  4. The GTS AXI Streaming IP sequences its internal blocks for reset entry. When the internal blocks are ready for reset, the GTS AXI Streaming IP asserts p<n>_subsystem_rst_rdy to the user reset controller.
  5. The user reset controller acknowledges to the subsystem that it is ready for reset by asserting p<n>_initiate_rst_req_rdy.
  6. The GTS AXI Streaming IP then asserts pld_warm_rst_rdy to HIP.
  7. HIP asserts p<n>_reset_status_n indicating the application logic needs to be in reset.
  8. The user reset controller asserts p<n>_subsystem_warm_rst_n, p<n>_axi_st_areset_n, and p<n>_axi_lite_areset_n.
Note: The Warm Reset flow is similar to Cold Reset flow, with the exception that p<n>_pin_perst_n and p<n>_subsystem_cold_rst_n are not asserted for warm reset.
Figure 41. Warm Reset Entry and Exit Sequence Timing Diagram

User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence

  1. Cold Reset is initiated by the user reset controller by the assertion of the p<n>_subsystem_rst_req.
  2. The GTS AXI Streaming IP sequences its internal blocks for reset entry. When the internal blocks are ready for reset, the GTS AXI Streaming IP asserts p<n>_subsystem_rst_rdy to user reset controller.
  3. User reset controller asserts p<n>_subsystem_cold_rst_n, p<n>_subsystem_warm_rst_n, p<n>_axi_st_areset_n, and p<n>_axi_lite_areset_n.
Figure 42. User Reset Sequencer Initiated Cold Reset Entry and Exit Sequence Timing Diagram

User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence

User reset controller triggered Warm Reset flow is the same as the user reset controller triggered Cold Reset flow, with the exception that the p<n>_subsystem_cold_rst_n is not asserted for this flow.

Figure 43. User Reset Sequencer Initiated Warm Reset Entry and Exit Sequence Timing Diagram
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