GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

7.9.1. Function Level Reset Received Interface

Table 50.  Function Level Reset Received Interface
Signal Name Direction Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) Clock Domain Description
p<n>_ss_app_st_flrrcvd_tvalid Output EP p<n>_axi_lite_clk When asserted, indicates a FLR request received from HOST. The signal is valid for one clock cycle.
p<n>_ss_app_st_flrrcvd_tdata[19:0] Output EP p<n>_axi_lite_clk

Valid when p<n>_ss_app_st_flrrcvd_tvalid assert.

  • Bit [2:0]: The PF Number of FLR Completion.
  • Bit [13:3]: Indicates child VF Number of parent PF indicated by PF Number.
  • Bit [14]: Indicates completion is from Virtual Function implemented in controller’s physical function.
  • Bit [19:15]: Reserved.

The figure below shows timing diagram for function level reset indication to the application.

The first command indicates FLR for Physical Function = 1 on slot = 0.

The second and third back-to-back indications are for VF, the p<n>_ss_app_st_flrrcvd_tdata[19:0] high indicates FLR is received for Virtual Function.

The fourth command signals FLR for PF=0.

Figure 59. Function Level Reset Received Interface