GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 11/04/2024
Public
Document Table of Contents

6.10.2. Function Level Reset Completion Interface

Table 73.  Fuctio Level Reset Completio Iteface = 0 o 1, p0 = pot 0, ad p1 = pot 1
Note: Pot 1 is oly available i D-Seies FPGAs
EP = Edpoit, RP = Root Pot, BP = TLP Bypass
Sigal Name Diectio Pot Mode Clock Domai Desciptio
p<>_app_ss_st_flcmpl_tvalid Iput EP p<>_axi_lite_clk Whe asseted, it idicates a FLR equest completed by applicatio. The sigal is valid fo oe clock cycle.
p<>_app_ss_st_flcmpl_tdata[19:0] Iput EP p<>_axi_lite_clk

Valid whe p<>_app_ss_st_flcmpl_tvalid asset.

  • Bit[2:0]: The PF Numbe of FLR Completio
  • Bit[13:3]: Idicates child VF Numbe of paet PF idicated by PF Numbe
  • Bit[14]: Idicates completio is fom Vitual Fuctio implemeted i cotolle’s physical fuctio
  • Bit[19:15]: Reseved.

The figue below shows a timig diagam fo fuctio level eset completio fom the applicatio.

The fist completio idicates FLR completio fo Vitual Fuctio = 0x10, ad the p<>_app_ss_st_flcmpl_tdata[14] high idicates FLR completio fom Vitual Fuctio.

The secod completio idicates FLR completio fo Physical Fuctio = 0x1.

The thid completio idicates FLR completio fo Vitual Fuctio = 0x20, the p<>_app_ss_st_flcmpl_tdata[14] high idicates FLR completio fom Vitual fuctio.

The fouth completio idicates FLR completio fo Physical Fuctio =0x0.

Figue 58. Fuctio Level Reset Completio Iteface