GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
Visible to Intel only — GUID: aqc1714120568249
Ixiasoft
Visible to Intel only — GUID: aqc1714120568249
Ixiasoft
7.6.2.3. PCI Express* Device Control and Status Register
Address: Offset 0x8
This register contains control and status bits for the Function.
Bit Location | Description | Attributes | Default |
---|---|---|---|
14:0 | Reserved | RsvdZ | 0 |
15 | Function-Level Reset. Writing a 1 into this bit position generates a Function-Level Reset for this Virtual Function if the FLR Capable bit of the Device Capabilities Register is set. This bit always reads as 0. |
RW | 0 |
16 | Reserved | RsvdZ | 0 |
17 | Non-Fatal Error Detected. | RW1C | 0 |
18 | Reserved | RsvdZ | 0 |
19 | Unsupported Request Detected. | RW1C | 0 |
20 | AUX Power Detected. | RO | 0 |
21 | Transaction Pending. Indicates that a Non-Posted request issued by this Virtual Function is still pending. |
RO | 0 |
31:22 | Reserved | RO | 0 |