Visible to Intel only — GUID: fvm1711414800145
Ixiasoft
Visible to Intel only — GUID: fvm1711414800145
Ixiasoft
7.4.2. Configuration Intercept Response Interface
The application must return the response for the request received on the Configuration Intercept Request interface using the Configuration Intercept Response interface. The GTS AXI Streaming IP is always ready to accept responses from the application. The application must provide response data with a valid qualifier.
This interface is applicable only when operating as Endpoint mode.
Signal Name | Direction | Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) | Clock Domain | Description |
---|---|---|---|---|
p<n>_app_ss_st_ciiresp_tvalid | Input | EP | p<n>_axi_lite_clk | The application asserts this signal for one clock to indicate that valid data is driven on the p<n>_app_ss_st_ciiresp_tdata bus. |
p<n>_app_ss_st_ciiresp_tdata[32:0] | Input | EP | p<n>_axi_lite_clk | Bit [31:0]: Overrides data from the application for the intercepted configuration request on the Configuration Intercept Request interface.
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The figure below shows timing diagram for back-to-back read and write requests.
The first request sends configuration read on the Configuration Intercept Request interface for all four bytes of register located at address=0x8.
The application decides not to intercept this configuration read and hence returns p<n>_app_ss_st_ciiresp_tvalid=1 together with p<n>_app_ss_st_ciiresp_tdata[32]=0 on the Configuration Intercept Respond interface.
After receiving the first response on the Configuration Intercept Respond interface, the second request sends configuration write for byte0, byte1, and byte2 of register located at address=0x4 with data value of 0xABC. The application decides to intercept this configuration write and hence return p<n>_app_ss_st_ciiresp_tvalid=1 together with p<n>_app_ss_st_ciiresp_tdata[32]=1 on the Configuration Intercept Respond interface. Additionally, the application provides the data (i.e., 0xDEF) to be used for the intercepted configuration write on the Configuration Intercept Respond interface through p<n>_app_ss_st_ciiresp_tdata[31:0].