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1. About Triple-Speed Ethernet Intel® FPGA IP for Agilex™ 5 devices
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
11. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Reset
4.1.11. PHY Management (MDIO)
4.1.12. Connecting MAC to External PHYs
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with Internal FIFO Buffers, and 1000BASE-X/SGMII 2XTBI PCS with Embedded PMA (GTS) Signals
6.1.5. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.6. 1000BASE-X/SGMII PCS Signals
6.1.7. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
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4.1.5. MAC Transmit and Receive Latencies
Altera uses the following definitions for the transmit and receive latencies:
- Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon® streaming interface.
- Receive latency is the number of clock cycles the MAC function takes to present the first bit on the Avalon® streaming interface after the bit was received on the network-side interface (MII/GMII/RGMII).
MAC Configuration | Latency (Clock Cycles) 3 4 | |
---|---|---|
Transmit | Receive | |
MAC with Internal FIFO Buffers 5 | ||
GMII in gigabit and cut-through mode | 30 | 112 |
MII in 100M and cut-through mode | 20 | 213 |
MII in 10M and cut-through mode | 17 | 211 |
RGMII in gigabit and cut-through mode | 35 | 112 |
RGMII in 10 Mbps and cut-through mode | 30 | 207 |
RGMII in 100 Mbps and cut-through mode | 26 | 205 |
MAC without Internal FIFO Buffers 6 | ||
GMII | 15 | 32 |
MII | 24 | 62 |
RGMII in gigabit mode | 16 | 32 |
RGMII in 100 Mbps | 17 | 78 |
RGMII in 10 Mbps | 18 | 78 |
Related Information
3 The clocks in all domains are running at the same frequency.
4 The numbers in this table are from simulation.
5 The data width is set to 32 bits
6 The data width is set to 8 bits.