AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

3.9.1. Running the Design Example

Here are the test operations you can perform on the AXI Streaming Intel® FPGA IP for PCI Express* design examples:

Table 21.  Test Operations Supported by the AXI Streaming Intel® FPGA IP for PCI Express*
Operations Required BAR Supported by the AXI Streaming Intel® FPGA IP for PCI Express*
PIO
0: Link test - 10 writes and reads 0 Yes
1: Write memory space 0 Yes
2: Read memory space 0 Yes