AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

A.3.1. R-Tile Completion Buffer Size

For R-Tile, the PCIe Hard IP implements Completion Buffers for Header and Data for each PCIe core/port. In Endpoint mode, when Completion credits are infinite, the user application needs to manage the number of outstanding requests according to the buffer size to prevent overflow and lost Completion packets.

Table 108.  R-Tile Completion Buffer Size
Completion Buffer Depth Width
Port 0 Cpl header 1024 NA
Port 0 Cpl data 2048 256
Port 1 Cpl header 256 NA
Port 1 Cpl data 1024 128
Port 2 Cpl header 128 NA
Port 2 Cpl data 512 64
Port 3 Cpl header 128 NA
Port 3 Cpl data 512 64