AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 7/08/2024
Public
Document Table of Contents

3.5. Instantiate and Connect the AXI Streaming Intel® FPGA IP for PCI Express* Interfaces

You can use the Quartus® Prime Platform Designer and IPs in the IP catalog, and/or use RTL to design to add any additional IPs, user logic required in the design and connect the IPs and user logic. You can also make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters. For Quartus generated design examples, the required IPs, clocking, reset and application logic to run basic traffic are already provided by the generated design.

Figure 19. Flow Diagram for Instantiating and Connecting the Interfaces in the AXI Streaming Intel® FPGA IP for PCI Express*