Parameterizable Macros for Intel® FPGAs Release Notes

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ID 782047
Date 7/05/2023
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Document Table of Contents x
1. Parameterizable Macros for Intel® FPGAs Release Notes
1. Parameterizable Macros for Intel® FPGAs Release Notes x
1.1. Simple Dual-Port RAM Parameterizable Macros v23.2 1.2. True Dual-Port RAM Parameterizable Macros v23.2 1.3. Asynchronous FIFO Parameterizable Macros v23.2 1.4. Synchronous FIFO Parameterizable Macros v23.2 1.5. Revision History for Parameterizable Macros for Intel FPGAs Release Notes
1. Parameterizable Macros for Intel® FPGAs Release Notes

1.2. True Dual-Port RAM Parameterizable Macros v23.2

Table 2.  True Dual-Port RAM Parameterizable Macros Parameter Changes
Intel® Quartus® Prime Version Change Description Impact
23.2

The following version 23.1 parameter names are updated in version 23.2. Use of these 23.1 parameter names causes an error in version 23.2 onward.

23.1 Parameter Name 23.2 Parameter Name
CLK_EN_IN_A IN_CLK_EN_A
CLK_EN_IN_B IN_CLK_EN_B
CLK_EN_OUT_A OUT_CLK_EN_A
CLK_EN_OUT_B OUT_CLK_EN_B
MEMORY_INIT_FILE INIT_FILE
OUT_DATA_A_ACLR OUT_DATA_ACLR_A
OUT_DATA_A_SCLR OUT_DATA_SCLR_A
OUT_DATA_B_ACLR OUT_DATA_ACLR_B
OUT_DATA_B_SCLR OUT_DATA_SCLR_B
OUT_DATA_REG_A_CLK OUT_DATA_REG_CLK_A
OUT_DATA_REG_B_CLK OUT_DATA_REG_CLK_B
READ_DURING_WRITE_A READ_DURING_WRITE_MODE_A
READ_DURING_WRITE_B READ_DURING_WRITE_MODE_B

The Intel® Quartus® Prime Compiler generates an error message for use of version 23.1 parameter names for the macros in this description.

Refer to the Parameterizable Macros for Intel FPGAs User Guide version 23.2 if migrating your design from version 23.1.

23.2

The following version 23.1 parameter names are obsolete from version 23.2 onward. Use of these 23.1 parameter names causes an error in version 23.2 onward:

  • ADDR_REG_B_CLK
  • BYTE_EN_REG_B
  • FORCE_TO_ZERO
  • IN_DATA_REG_B_CLK
  • MEMORY_OPTIMIZATION
  • RAM_BLOCK_TYPE
  • READ_DURING_WRITE_MODE_MIXED_PORTS

The Intel® Quartus® Prime Compiler generates an error message for use of these obsolete parameter names starting in version 23.2.

Refer to the Parameterizable Macros for Intel FPGAs User Guide version 23.2 if migrating your design from version 23.1.

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