Parameterizable Macros for Intel® FPGAs Release Notes

Download PDF
ID 782047
Date 7/05/2023
Public
Document Table of Contents
Document Table of Contents x
1. Parameterizable Macros for Intel® FPGAs Release Notes
1. Parameterizable Macros for Intel® FPGAs Release Notes x
1.1. Simple Dual-Port RAM Parameterizable Macros v23.2 1.2. True Dual-Port RAM Parameterizable Macros v23.2 1.3. Asynchronous FIFO Parameterizable Macros v23.2 1.4. Synchronous FIFO Parameterizable Macros v23.2 1.5. Revision History for Parameterizable Macros for Intel FPGAs Release Notes
1. Parameterizable Macros for Intel® FPGAs Release Notes

1.1. Simple Dual-Port RAM Parameterizable Macros v23.2

Table 1.  Simple Dual-Port RAM Parameterizable Macros Parameter Changes
Intel® Quartus® Prime Version Change Description Impact
23.2

The following version 23.1 parameter names are updated in version 23.2. Use of these 23.1 parameter names causes an error in version 23.2 onward.

23.1 Parameter Name 23.2 Parameter Name
ADDR_REG_B_ACLR ADDR_ACLR_B
ADDR_REG_B_CLK ADDR_REG_CLK_B
DATA_REG_B_ACLR OUT_DATA_ACLR_B
DATA_REG_B_CLK OUT_DATA_REG_CLK_B
DATA_REG_B_SCLR OUT_DATA_SCLR_B

The Intel® Quartus® Prime Compiler generates an error message for use of version 23.1 parameter names for the macros in this description.

Refer to the Parameterizable Macros for Intel FPGAs User Guide version 23.2 if migrating your design from version 23.1.

23.2

The following version 23.1 parameter names are obsolete from version 23.2 onwards. Use of these 23.1 parameter names in version 23.2 and beyond causes an error:

  • ENABLE_COHERENT_READ
  • ENABLE_FORCE_TO_ZERO
  • RAM_BLOCK_TYPE

The Intel® Quartus® Prime Compiler generates an error message for use of the obsolete parameter names starting in version 23.2.

Refer to the Parameterizable Macros for Intel FPGAs User Guide version 23.2 if migrating your design from version 23.1.

Related Information
Level Two Title