Parameterizable Macros for Intel® FPGAs Release Notes

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ID 782047
Date 7/05/2023
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Document Table of Contents x
1. Parameterizable Macros for Intel® FPGAs Release Notes
1. Parameterizable Macros for Intel® FPGAs Release Notes x
1.1. Simple Dual-Port RAM Parameterizable Macros v23.2 1.2. True Dual-Port RAM Parameterizable Macros v23.2 1.3. Asynchronous FIFO Parameterizable Macros v23.2 1.4. Synchronous FIFO Parameterizable Macros v23.2 1.5. Revision History for Parameterizable Macros for Intel FPGAs Release Notes
1. Parameterizable Macros for Intel® FPGAs Release Notes

1.4. Synchronous FIFO Parameterizable Macros v23.2

Table 4.  Synchronous FIFO Parameterizable Macros Parameter Changes
Intel® Quartus® Prime Version Change Description Impact
23.2

The following version 23.1 parameter name is obsolete in version 23.2. Use of this 23.1 parameter name causes an error in version 23.2 onward.

23.1 Parameter Name 23.2 Parameter Name
RAM_BLOCK_TYPE (AUTO, MLAB, M20K) (obsolete)

The following version 23.1 allowable values for the MAXIMUM_DEPTH parameter are changing in version 23.2. Use of these 23.1 parameter values causes an error in version 23.2 onward.

23.1 Parameter Values 23.2 Parameter Values
Must comply with 2^ADDR_WIDTH_A or 2^ADDR_WIDTH_B

AUTO, 32, 64, 128, 256, 512, 1024, 2048 (default), 4096, 8192, or 16384

The Intel® Quartus® Prime Compiler generates an error message for use of the version 23.1 parameter names or values for the macros in this description.

Refer to the Parameterizable Macros for Intel FPGAs User Guide version 23.2 if migrating your design from version 23.1.

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