High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Release Notes

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ID 773268
Date 11/04/2024
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Document Table of Contents x
1. High Bandwidth Memory (HBM2E) Interface FPGA IP Release Notes
1. High Bandwidth Memory (HBM2E) Interface FPGA IP Release Notes x
1.1. HBM2E Interface FPGA IP v6.0.0 1.2. HBM2E Interface Intel® FPGA IP v3.0.0 1.3. HBM2E Interface Intel® FPGA IP v2.0.0 1.4. HBM2E Interface Intel® FPGA IP v1.3.0 1.5. HBM2E Interface Intel® FPGA IP v1.2.0
1. High Bandwidth Memory (HBM2E) Interface FPGA IP Release Notes

1. High Bandwidth Memory (HBM2E) Interface FPGA IP Release Notes

Updated for:
Intel® Quartus® Prime Design Suite 24.3
IP Version 6.0.0

If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Quartus® Prime Design Suite Update Release Notes.

Intel® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.

The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Section Content
HBM2E Interface FPGA IP v6.0.0
HBM2E Interface Intel FPGA IP v3.0.0
HBM2E Interface Intel FPGA IP v2.0.0
HBM2E Interface Intel FPGA IP v1.3.0
HBM2E Interface Intel FPGA IP v1.2.0

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