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1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
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7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2023.07.14 | 23.2 | 1.3.0 | In the Architecture chapter, corrected a text label in the Block Diagram of Intel Agilex 7 M-Series HBM2E Implementation figure in the Intel Agilex 7 M-Series UIB Architecture topic. |
2023.06.26 | 23.2 | 1.3.0 |
|
2023.04.21 | 23.1 | 1.2.0 | Initial release. |